Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 87
UG074 (v2.2) February 22, 2010
Host Interface
R
program the MIIMWRDATA register. Writing to the address of the MIIMCNTL register
starts the MDIO read or write transaction using the physical and register address in the
DCR dataRegLSW register.
The host interface interrupt request registers (IRENABLE and IRSTATUS) and the contents
of the registers are shown in Table 3-26 and Table 3-27. The MIIMWRDATA register is
shown in Table 3-28.
Table 3-26: Interrupt Status Register IRSTATUS
Address
Code
MSB
LSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0x3A0
RESERVED
CFG WST1
CFG RST1
AF WST1
AF RST1
MIIM WST1
MIIM RST1
STAT RST1
RSVD
CFG WST0
CFG RST0
AF WST0
AF RST0
MIIM WST0
MIIM RST0
STAT RST0
Bit Description Ethernet MAC Default Value
[0:16] Reserved. – 0
[17] Configuration Write Interrupt Request bit. EMAC1 0
[18] Configuration Read Interrupt Request bit. EMAC1 0
[19] Address Filter Write Interrupt Request bit. EMAC1 0
[20] Address Filter Read Interrupt Request bit. EMAC1 0
[21] MDIO Write Interrupt Request bit. EMAC1 0
[22] MDIO Read Interrupt Request bit. EMAC1 0
[23] Statistics IP Read Interrupt Request bit.
(1)
EMAC1 0
[24] Reserved. – 0
[25] Configuration Write Interrupt Request bit. EMAC0 0
[26] Configuration Read Interrupt Request bit. EMAC0 0
[27] Address Filter Write Interrupt Request bit. EMAC0 0
[28] Address Filter Read Interrupt Request bit. EMAC0 0
[29] MDIO Write Interrupt Request bit. EMAC0 0
[30] MDIO Read Interrupt Request bit. EMAC0 0
[31] Statistics IP Read Interrupt Request bit.
(1)
EMAC0 0
Notes:
1. For more information on Statistics IP, see “Interfacing to an FPGA Fabric-Based Statistics Block” in Chapter 6.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English