YOKOGAWA DLM4038 User Manual

5-223
IM DLM4038-17EN
Commands
1
2
3
4
5
6
App
Index
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:BRATe
Function Sets or queries the bit rate for user-defined bus
signal analysis.
Syntax
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:BRATe {<NRf>}
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:BRATe?
<x> = 1 to 4
<NRf> = 1000 to 50000000 (bps)
Example
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:B
RATE 1000
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:B
RATE?
-> :SERIALBUS1:SPATTERN:ANALYZE:SETU
P:BRATE 1000
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk?
Function Queries all clock signal settings for user-defined
bus signal analysis.
Syntax
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk?
<x> = 1 to 4
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:MODE
Function Sets or queries the clock signal enable or disable
status for user-defined bus signal analysis.
Syntax
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:MODE {<Boolean>}
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:MODE?
<x> = 1 to 4
Example
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
LOCK:MODE ON
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
LOCK:MODE?
-> :SERIALBUS1:SPATTERN:ANALYZE:SETU
P:CLOCK:MODE 1
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:POLarity
Function Sets or queries the clock signal slope for user-
defined bus signal analysis.
Syntax
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:POLarity {FALL|RISE}
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:POLarity?
<x> = 1 to 4
Example
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
LOCK:POLARITY FALL
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
LOCK:POLARITY?
-> :SERIALBUS1:SPATTERN:ANALYZE:SETU
P:CLOCK:POLARITY FALL
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:SOURce
Function Sets or queries the clock signal for user-defined
bus signal analysis.
Syntax
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:SOURce {<NRf>}
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CLOCk:SOURce?
<x> = 1 to 4
<NRf> = 1 to 8
Example
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
LOCK:SOURCE 1
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
LOCK:SOURCE?
-> :SERIALBUS1:SPATTERN:ANALYZE:SETU
P:CLOCK:SOURCE 1
Description The clock signal that you can specify varies
depending on the
:SERialbus<x>:SPATtern[
:ANALyze]:SETup:DATA:SOURce
setting.
For details, see the DLM4000 User’s Manual.
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CS?
Function Queries all chip select signal settings for user-
defined bus signal analysis.
Syntax
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CS?
<x> = 1 to 4
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CS:ACTive
Function Sets or queries the chip select signal active state
for user-defined bus signal analysis.
Syntax
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CS:ACTive {HIGH|LOW}
:SERialbus<x>:SPATtern[:ANALyze]:SET
up:CS:ACTive?
<x> = 1 to 4
Example
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
S:ACTIVE HIGH
:SERIALBUS1:SPATTERN:ANALYZE:SETUP:C
S:ACTIVE?
-> :SERIALBUS1:SPATTERN:ANALYZE:SETU
P:CS:ACTIVE HIGH
5.25 SERialbus Group

YOKOGAWA DLM4038 Specifications

General

Brand	YOKOGAWA
Model	DLM4038
Category	Test Equipment
Language	English