ZiLOG Z8 Technical Manual

11.3 COUNTER/TIMER OPERATION
Under software control, counter/timers are started
and stopped via the Timer Mode register (%Fl) bits
DO-D3 (Figure 11-6). Each counter/timer is asso-
ciated with a Load bit and an Enable Count bit.
11.3.1 load and Enable Count Bits
Setting the Load bit (DO to 1 for TO and D2 to 1
for T 1)
transfers the initial value in the pre-
scaler and the counter/timer registers into their
respective down-counters. The next internal clock
resets bits DO and D2 to 0, readying the Load bit
for the next load operation. The initial values
may be loaded into the down-counters at any time.
If the counter/timer is running, it continues to
do so and starts the count over with the initial
value. Therefore, the Load bit actually functions
as a software re-trigger.
The counter/timers remain at rest as long as the
Enable Count bits Dl and 0
3
are both O. To enable
counting, the Enable Count bit (0
1
for TO and D3
for T 1) must be set to 1. Counting actually
starts when the Enable Count bit is written by an
instruction. The first decrement occurs four
internal clock periods after the Enable Count bit
has been set.
The Load and Enable Count bits can be set at the
same time. For example, using the instruction OR
TMR /1%03 sets both DO and 0
1
of TMR to 1. This
loads the initial values of PRE
O
and TO into their
respective counters and starts the count after the
M2T2 machine state after the operand is fetched
(Figure 11-7).
11.3.2 Prescaler Operations
During counting, the programmed clock source
drives the prescaler 6-bit counter. The counter
is counted down from the value specified by bits
D
2
-D
7
of the corresponding prescaler register,
PRE
O
or PRE
1
(Figure 11-8). When the prescaler
counter reaches its end-of-count, the initial
value is reloaded and counting continues. The
prescaler never actually reaches O. For example,
if the prescaler is set to divide by 3, the ~ount
sequence is:
3-2-1-3-2-1-3-2 ••••
Each time the prescaler reaches its end-of-count a
carry is generated, which allows the counter/timer
to decrement by one on the next timer clock
input. When the counter/timer and the prescaler
3047-016 3047-066. 3047-017
Counter/Timers
both reach their end-of-count, an interrupt
request is generated -- IRQ
4
for
TO and 1RQ5 for
T
1
• Depending on the counting mode selected, the
counter/timer will either come to rest with its
value at ~oOO (Single-Pass mode) or the initial
value will be automatically reloaded and counting
will continue (Continuous mode).
R241 TMR
Timer Mode Register
(% F1; Read/Write)
~
L 0 = NO FUNCTION
1 = LOAD To
o = DISABLE To COUNT
1 = ENABLE To COUNT
o = NO FUNCTION
1 = LOAD T1
'-- ____ 0 = DISABLE T1 COUNT
1 = ENABLE T1 COUNT
Figure 11-6. Timer Hode Register
M3
TMR IS WRITIEN
COUNTERITIMERS
ARE LOADED
1ST DECREMENT
OCCURS FOUR
CLOCKS
LATER
Figure 11-7. Starting The Count
R243 PRE1
Prescaler 1 Register
(% F3; Write Only)
R245 PREO
Prescaler 0 Register
(% F5; Write Only)
L
COUNT MODE
1 = T1 MODULO·N
o = T1 SINGLE·PASS
Figure 11-8. Counting Hodes
11-3

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English