EasyManuals Logo

ZiLOG Z8 Technical Manual

ZiLOG Z8
166 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #130 background imageLoading...
Page #130 background image
Counter/Timers
The
counting
modes
are
controlled
by
bit
00
of
PRE
O
and
PRE
1
,
with 00
cleared
to
0
for
Single-pass
counting
mode
or
set
to
1
for
Continuous
mode.
The
counter/timers
can be
stopped
at
any time
by
setting
the
Enable Count
bit
to
0,
and
restarted
by
setting
it
back
td
1.
The
counter/timer
will
continue
its
count
value
at
the
time
it
was
stopped.
The
current
value
in
the
counter/timer
(TO
or T
1
) can be
read
at
any
time
without
affecting
the
counting
operation.
New
initial
values
can be
written
to
the
prescaler
or
the
counter/timer
registers
at
any
time.
These
values
will
be
transferred
to
their
respective
down-counters
on
the
next
load
operation.
If
the
counter/timer
mode
is
Continuous,
the
next
load
occurs
on
the
timer
clock
following
an
end-of-count.
New
initial
values
should
be
written
before
the
desired
load
operation,
since
the
prescalers
always
effectively
operate
in
Continuous count
mode.
The
time
interval
(i)
until
end-of-count,
is
given
by
the
equation
i:txpxv
in
which t
is
8
divided
by
XTAL
frequency,
p
is
the
prescaler
value
(1
-
64),
and v
is
the
counter/timer
value
(1
-
256).
It
should
be
apparent
that
the
prescaler
and
counter/timer
are
true
divide-by-n
counters.
11.4
TOUT
MODES
The
Timer
Mode
register
TMR
(%F1)
(Figure
11-10)
is
used
in
conjunction
with
the
Port
3
Mode
register
P3M
(%F7)
(Figure
11-9)
to
configure
P3
6
for
TOUT
operation.
In
order
for
TOUT
to
function,
P3
6
must be
defined
as
an
output
line
by
setting
P3M
bit
05
to
O.
Output
is
controlled
by
one
of
the
counter/timers
(TO
or T
1
)
or
the
internal
clock.
The
counter/timer
to
be
output
is
selected
by
TMR
bits
07
and
06.
TO
is
selected
to
drive
the
TOUT
line
by
setting
07
to
0 and 06
to
1.
Likewise,
T1
is
selected
by
setting
07 and 06
to
1
and
0
respectively.
The
counter/timer
TOUT
mode
is
turned
off
by
setting
TMR
bits
07 and 06
both
to
0,
freeing
P3
6
to
be a
data
output
line.
T
OUT
is
initialized
to
a
logic
1 whenever
the
TMR
Load
bit
(00
for
TO
or
02
for f
1
)
is
set
to
1.
R247
P3M
Port 3 Mode Register
(%
F7;
Write Only)
o P3l = INPUT
(TIN)
P36
= OUTPUT
(TOUT)
1 P3l = DAV2/RDY2
P36
= RDY2IDAV2
Figure
11-9.
Port
J
Mode
Register
TOUT
Operation
R241
TMR
Timer Mode Register
(%
F1;
Read/Write)
TOUT
MODES I
TOUT
OFF =
00
To
OUT =
01
Tl
OUT = 10
INTERNAL
CLOCK OUT =
11
L
0 = NO FUNCTION
1 = LOAD
To
o = NO FUNCTION
1 = LOAD
Tl
Figure
11-10.
Timer
Mode
Register
TOUT
Operation
11-4
3047-010,3047-018

Table of Contents

Other manuals for ZiLOG Z8

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ZiLOG Z8 and is the answer not in the manual?

ZiLOG Z8 Specifications

General IconGeneral
BrandZiLOG
ModelZ8
CategoryDesktop
LanguageEnglish

Related product manuals