ZiLOG Z8 Technical Manual

Counter/Timers
IRQ4 TMR
(TO ENO·OF·COUNT) -----, 07-06 = 01
,....- ....
IRQS ~TMR
(T1 ENO·OF·COUNT) 07-06 = 10
figure 11-11. Counter/Timers Output Via TOUT
INTERNAL
CLOCK
Figure 11-12. Internal Clock Output Via TOUT
At end-of-count, the interrupt request line (IRQ4
or IRQ5)' clocks a toggle flip-flop. The output
of this flip-flop drives the TOUT line, P3
6
•
In
all cases, when the selected counter/timer reaches
its end-of-count, TOUT toggles to its opposite
state (Figure 11-11). If, for example, the
counter/timer is in Continuous counting mode,
T OUT will have a 50% duty cycle output. This
duty cycle can easily be controlled by varying the
initial values after each end-of-count.
The internal clock can be selected as output
instead of TO or T1 by setting TMR bits D7 and D6
both to 1. The internal clock (XTAL frequency/2)
is then direct~y output on P3
6
(Figure 11-12).
R241 TMR
Timer Mode Register
(% F1; Read/Write)
TIN MODES
EXTERNAL CLOCK INPUT = 00
GATE INPUT = 01
TRIGGER INPUT = 10
(NON·RETRIGGERABLE)
TRIGGER INPUT
= 11
(RETRIGGERABLE)
While programmed as TOUT' P36 cannot be modified
by a wr ite to port register P3. However, the ZS
software can examine P3
6
's current output by
reading the port register.
Figure 11-13. Timer Mode Register TIN Operation
11.5 TIN tD>ES
The Timer Mode register TMR (%F1) (Figure 11-13)
is used in conjunction with the Prescaler register
PRE
1
(%F3) (Figure 11-14) to configure P3
1
as
fIN.
TIN is used in conjunction with T1 in
one of four modes:
• External clock input
• Gated internal clock
• Triggered internal clock
• Retriggerable internal clock
3047·083.3047·067.3047·019.3047·020
R243 PRE1
Prescaler 1 Register
(% F3; Write Only)
L
CLOCK SOURCE
1 = T1 INTERNAL
o = T1 EXTERNAL (TIN)
Figure 11-14. Prescaler 1 TIN Operation
11-5

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English