ZiLOG Z8 Technical Manual

Counter/Timers
The counter/timer clock source must be configured
for external by setting PRE
1
bit 02 to O. The
Timer Mode register bits Os and 04 can then be
used
to select the desired TIN operation.
For T 1 to start counting as a result of a TIN
input, the Enable Count bit 03 in TMR must be set
to 1. When using T IN as an external clock or a
gate input, the initial values must be loaded into
the down-counters by setting the Load bit 02 in
TMR to a 1 before counting begins. In the
descr iptions of T IN that follow, it is assumed
that the programmer has performed these opera-
tions. Initial values are automatically loaded
in Trigger and Retrigger modes so software loading
is unnecessary.
It is suggested that P3
1
be configured as an input
line by setting P3M bit Os to 0 although TIN is
still functional if P3
1
is configured as a hand-
shake input.
Each High-to-Low transition on TIN generates
interrupt request IRQ2' regardless of the selected
T IN mode or the enabled/disabled state of T 1 •
IRQ2 must therefore be masked or enabled according
to the needs of the application.
T'N -1
P31
H
D
CLOCK
.IU1...
i
INTERNAL
CLOCK
1
D
j
11.5.1 External Clock Input Hode
The T IN External Clock Input mode (TMR bits Os
and 04 both set to 0) supports counting of
external events, where an event is considered to
be a High-to-Low transition on TIN (Figure
11-1S). occurrence (Single-Pass mode) or on every
nth occurrence (Continuous mode) of that event.
11.5.2 Gated Internal Clock Hode
The TIN Gated Internal Clock mode (TMR bits Os
and 04 set to 0 and 1 respectively) measures the
duration of an external event. I n this mode, the
T1 prescaler is driven by the internal timer
clock, gated by a High level on TIN (Figure
11-16). T1 counts while TIN is High and stops
counting while T IN is Low. Interrupt request
IRQ2 is generated on the High-to-Low transition of
TIN' signaling the end of the gate input.
Interrupt request IRQS is generated if T1 reaches
its end-of-count.
TMR
D5-D4
= 00
1
1
·1
PRE1 T1
~
IROS
IR02
Figure 11-15. External Clock Input Hode
~~ ________ ~ INTERNAL
CLOCK
TMR
D5-D4
= 01
~P_R_E_1 ..... _T_1_ .. ~ 'Ra,
-!-4
IR02
Figure 11-16. Gated Clock Input Mode
11-6
3047-085, 3047-086

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English