ZiLOG Z8 Technical Manual

Serial I/O
After a full character has been assembled in the
Shift register, the data is transferred to the
receiver's buffer, SID U~FO), and interrupt
request IRQ3 is generated. The shift clock is
stopped and the Shift register reset to all 1 s.
The start bit detection circuitry begins monitor-
ing
the data input for the next start bit. This
cycle allows the receiver to synchronize on the
center of the bit time for each incoming charac-
ter.
12.3.2 Overwrites
Although the receiver is buffered, it is not pro-
tected from being overwritten, so the software
must read the SID register within one character
time after the interrupt request. The Z8 does not
have a flag to indicate this overrun condition.
If polling is used, the IRQ3 bit in the Interrupt
Request register must be reset by software.
12.3.3 Framing Errors
Framing error detection is not supported by the
receiver hardware, but by responding to the inter-
rupt request within one character bit time, tho
software can test for a stop bit at P30. Port 3
bits are always readable, which facilitates break
detection. For example, if a null character is
received, testing P30 results in a 0 being read.
Received Oata
(No Parity)
12.3.4 Parity
The data format supported by the receiver must
have a
start bit, eight data bits, and at least
one stop bit. If parity is on, bit 07 of the data
received will be replaced by a Parity Error flag.
A parity error sets 07 to 1; otherwise, D7 is set
to O. Figure 12-8 shows these data formats.
The Z8 hardware supports odd parity only, which is
enabled by setting Port 3 Mode register bit D7 to
1 (Figure 12-9). If even parity is required, the
Parity mode should be disabled (i.e. P3M 07 set to
0), and software must calculate the received
data's parity.
12.4 TRANSMITTER OPERATION
The transmitter consists of a transmitter buffer
(SID (%FO», a parity generator, and associated
control logic. The transmitter block diagram is
shown as part of Figure 12-1.
After a hardware reset or after a character has
been
transmitted, the transmitter is forced to a
marking
state (output always High) until a charac-
ter is loaded into the transmitter buffer, SID
(%FO). The transmitter is loaded by specifying
the SID as the destination register of any
instruction.
I SP I 0
7
1 0
6
1 0
5
1 0
4
1 0
3
1 0
2
1 0
1
1 0
0
1 ST I
Received Oata
(With Parity)
I
LSTART BIT
'-------- EIGHT OATA BITS
L... ------------ONE STOP BIT
I SP 1 P 1 0
6
1 0
5
1 0
4
1 0
3
1 O
2
\
0
1
1 0
0
\ ST I
II,
__ LSTARTBIT
'-------SEVEN OATA BITS
PARITY
ERROR FLAG
L--------------ONE STOP BIT
Figure 12-8. Receiver Data Formats
12-4
2037·009

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English