ZiLOG Z8 - Processor Flags and Status

Serial I/O
12.5 RESEr CONH T UWS
A fter a hardware reset, the Serial I/O register
contents are undefined, and Serial mode and parity
are disabled. Figures 12-11 and 12-12 show the
binary reset values of the Serial I/O register and
its associated mode register P3M.
R240 SID
Serial 110 Register
(% FO; Read/Write)
1?1?1?1?1?!?I?ld
1 .... _____ SERIAL DATA (Do = LSB)
12-6
Figure 12-11. Serial I/O Register Reset
R247 P3M
Port 3 Mode Register
(% F78; Write Only)
1010101010101 101
L=
0 PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
o P32 = INPUT P35 = OUTPUT
1 P32
= DAVO/RDYO P35 = RDYO/DAVO
o 0 P33 = INPUT P34 = OUTPUT
1-- ____ ~ ~} P33 = INPUT P34 = OM
1 1 P33 = DAV1/RDY1 P34 = RDY1IDAV1
1-- _______ 0 P31 = INPUT (TIN) P36 = OUTPUT (TOUT)
1 P31 = DAV2/RDY2 P36 = RDY2/DAV2
'---------- ~ ~~~ ~ kN:R~lL IN ~~~ ~ ~~~~~T OUT
L..- __________ ~ ~!~:i~ g~F
Figure 12-12. Port 3 Register Reset
3047-029, 3047-030