ZiLOG Z8 - Page 49

DA
dst
Instruction format:
Cycles
DA
Decimal Adjust
OPC
(Hex)
Address Mode
dst
~ ______ OP_C ______ ~I I~ _______ d_s_t ______ ~
8 40
41
R
IR
Operation:
Flags:
dst <-- DA dst
The destination operand is adjusted to form two 4-bit BCD digits following a binary
addition or subtraction operation on BCD encoded bytes. For addition (ADD, ADC), or
subtraction (SUB, SBC), the following table indicates the operation performed:
Bits 4-7
Bits 0-3 N&..ber
Carry Value H Flag Value Added
Carry
Instruction Before DA (Hex) Before DA
(Hex) To Byte After DA
0
0-9
0
0-9
00
0
0
0-8
0
A-F
06
0
ADD
0
0-9
1 0-3
06
0
ADC 0
A-F
0 0-9
60
1
0
9-F
0 A-F
66 1
0
A-F
1
0-3
66
1
1
0-2 0 0-9
60
1
1
0-2
0
A-F
66 1
1
0-3
1
0-3
66
1
SUB
0 0-9
0
0-9
00 0
SBC
0 0-8 1 6-F
FA
0
1
7-F
0
0-9
AO
1
1
6-F
1 6-F
9A 1
If the destination operand is not the result of a valid addition or subtraction of
BCD digits, the operation is undefined.
C: Set if there is a carry from the most significant bit; cleared otherwise (see
table above)
Z Set if the result is 0; cleared otherwise
V Undefined
5
Set if the result bit 7 is set; cleared otherwise
H Unaffected
D Unaffected
5-15