ZiLOG Z8 Technical Manual

TeM
Test Complement Under Mask
TCH dst,src
Instruction Fo~at:
ope
ope
ope
Operation:
Flags:
EX8lllple:
Note:
5-48
OPC
Address Mode
Cycles
(Hex)
dBt
src
6
62
r
r
6 63
r
lr
I I
dst src
I
10 64 R R
10 65 R lR I I
src
I I
dst
src
10 66 R
1M
10 67 lR 1M
I
I
dst
I
I
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical "1"
value. The bits to be tested are specified by setting a 1 bit in the corresponding
position of the source operand (mask). The TeM statement complements the destination
operand, which is then ANDed with the source mask. The Zero (Z) flag can then be
checked
to determine the result. When the TeM operation is complete, the destination
location still contains its original value.
C: Unaffected
Z: Set if the result is zero; cleared otherwise
V: Always reset to 0
S: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
0: Unaffected
If the register named TESTER contains ~F6 (11110110) and the register named MASK
contains ~06 (00000110), that is, bits 1 and 2 are being tested for a 1 value, the
statement
TeM TESTER, MASK
complements TESTER (to 00001001) and then do a logical AND with register MASK,
resulting in ~OO. A subsequent test of the Z flag,
JP Z,plabel
causes a transfer of program control. At the end of this sequence, TESTER still
contains ~F6.
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E src/dst

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English