ZiLOG Z8 Technical Manual

",-
TM
dst,src
Instruction for.at:
ope
ope
ope
Operation:
flags:
Example:
Note:
TM
Test Under Mask
OPC
Address Hade
Cycles
(Hex)
dst src
I
I
dst arc 6
72
r r
6 73
r
Ir
I I
src
I I
dst
10
74
R R
10 75 R IR
I
I
dst
I I
arc
10 76 R 1M
10 77 IR 1M
dst AND src
This instruction tests selected bits in the destination operand for a logical "0"
value. The bits to be tested are specified by setting a 1 bit in the corresponding
position of the source operand (mask), which is ANDed with the destination operand.
The Z flag can be checked to determine the result. When the TM operation is
complete, the destination location still contains its original value.
c: Unaffected
Z:
Set if the result is zero; cleared otherwise
V: Always reset to 0
S: Set if the result bit 7 is set; cleared otherwise
H: Unaffected
D: Unaffected
If the register named TESTER contains %F6 (11110110) and the register named MASK
contains %06 (00000110), that is, bits 1 and 2 are being tested for a 0 value, the
statement
TM TESTER, MASK
results in the value %06 (00000110). A subsequent test for nonzero
JP NZ, plabe 1
causes a transfer of program control. At the end of this sequence, TESTER still
contains %F6. The Z and S flags are cleared.
When used to specify a 4-bit working-register address, address modes R or IR use the
format:
E src/dst
5-49

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English