ABB Relion REC670 - 15.12 Elapsed time integrator with limit transgression and overflow supervision TEIGAPC

IEC09000695_2_en.vsd
IEC09000695 V2 EN-US
Figure 182: Example designation, serial execution number and cycle time for logic
function
IEC09000310-1-en.vsd
IEC09000310 V1 EN-US
Figure 183: Example designation, serial execution number and cycle time for logic
function that also propagates timestamp and quality of input signals
The execution of different function blocks within the same cycle is determined by the order of
their serial execution numbers. Always remember this when connecting two or more logical
function blocks in series.
Always be careful when connecting function blocks with a fast cycle time to
function blocks with a slow cycle time.
Remember to design the logic circuits carefully and always check the execution
sequence for different functions. In other cases, additional time delays must be
introduced into the logic schemes to prevent errors, for example, race between
functions.
15.7 Fixed signal function block FXDSIGN
IP15080-1 v2
15.7.1 Identification
SEMOD167904-2 v2
Function description
IEC 61850
identification
IEC 60617
identification
ANSI/IEEE C37.2
device number
Fixed signals FXDSIGN - -
Section 15 1MRK 511 358-UEN A
Logic
364
Application manual