Chapter 8: Theory of Operation
Attenuator Theory
8–7
Attenuator Theory
The channel input signals are conditioned by the channel attenuator assemblies. There are four
completely independent attenuators on each assembly, but one channel can be routed in the
preamp/multiplexer hybrid to drive both channel outputs for sample rate doubling purposes.
Each channel contains passive attenuators, an impedance converter, and a programmable gain
amplifier. There are two identical outputs for each channel: one to drive the ADC hybrids and
one to drive the trigger circuitry.
After the passive attenuators, the signal is split into high-frequency and low-frequency
components. Low-frequency components are amplified on the main assembly where they are
combined with the offset voltage. The ac coupling is implemented in the low-frequency amplifier.
The high- and low-frequency components of the signal are recombined and applied to the input
FET of the impedance converter. The FET provides a high impedance load for the input
attenuators and a low impedance drive for a buffer, which drives 50 Ω.
Acquisition Theory
The acquisition system includes two major sections. One is the acquisition board, which
conditions, stores, and processes the input signals. The other is the A1 interface board, which
provides the interface from the acquisition to the motherboard and display, and also interfaces
the motherboard to the front-panel keyboard.
Acquisition Board
The acquisition circuitry samples, digitizes, and stores the signals from the channel attenuators.
The four channels are identical. The trigger signals synchronize acquisition through the trigger
and time base circuitry. A reference oscillator and the time base provide the base sample rates.
ADC The Agilent Technologies Infiniium Oscilloscope ADC provides all of the sampling,
digitizing, and high-speed waveform storage. Each ADC contains two 2 GSa/s ADCs. They
can be run in phase to increase resolution, or out-of-phase to sample at 4 GSa/s. The ADC
includes a delay-locked loop to synchronize the sample clock to the 125 MHz timebase
reference clock. For sample rates < 2 GSa/s, data is decimated.
Trigger There are four main trigger circuits: Trigger Conditioning, Analog Comparators, a
Trigger Multiplexer, and Logic Trigger. Trigger signals from the channel are fed to the analog
trigger comparators and the trigger conditioning circuit. The trigger conditioning circuitry
selects dc, ac, low-frequency reject, high-frequency reject, and noise reject (hysteresis)
modes and sets the trigger levels. The trigger multiplexer selects the trigger modes, such as
edge, glitch, and pattern trigger.
The channel triggers are sent to the Logic Trigger. The logic trigger provides the advanced
triggering functions, such as holdoff, delay, and pattern duration and range. The data delay and
clock delay timers are used to implement trigger functions that require timing between 1.5 and
20 ns.
The auxiliary trigger, which cannot be displayed on screen, is compared to the trigger level setting
in a separate circuit. The line sync trigger line from the power supply is combined in a multiplexer
with the TV trigger and the high frequency reject comparators before being sent to the analog
trigger.
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