4. Interfacing to the world 51
Figure 4.10: Connecting a LV-TTL signal to input port P1+
to the ”+” is therefore detected as logical ”1” when its level is at least 0.5 V higher than ”-” reference sig-
nal. Following table shows how to congure the threshold level in NECTA with 24 V tolerant I/O, using
the properties PIOHighVoltageOut and PIOHighThreshold.
Input maximum Voltage PIOHighVoltageOut PIOHighThreshold Reference Voltage
3.3 V False False 1.49 V
5 V True False 2.25 V
5 V to 24 V True True 5 V
Table 4.3: Single ended ”-” input voltage value
Note
Threshold level settings are common for all input ports.
Warning
When an input port is connected to a LV-CMOS/TTL signal its input termina-
tion must be kept disabled; otherwise, the input signal cannot be correctly de-
tected.
Caution
Input signals must never exceed +30 V on NECTA with 24 V tolerant I/O.
Input signals must never exceed +6 V on NECTA with 5 V tolerant I/O.