ASIX AX99100 - Page 32

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AX99100
PCIe to Multi I/O Controller
INT Mask (0x54~0x53)
Bit
Description
3:0
Setting INT A bit mapping (0x1) for Function 0.
Hardware Default value: 0x1.
7:4
Setting INT B bit mapping (0x2) for Function 1.
Hardware Default value:
0x0: for LB mode.
0x2: Others.
11:8
Setting INT C bit mapping (0x4) for Function 2.
Hardware Default value:
0x0: For LB and SPI mode.
0x4: Others.
15:12
Setting INT D bit mapping (0x8) for Function 3.
Hardware Default value:
0x0: For LB and PP mode.
0x8: Others.
Port Disable Register (0x55)
Bit
Description
0
XCVR Polarity Selection.
1: XCVR is active Low when AX99100 enter L2(D3) power saving mode
0: XCVR is active High when AX99100 enter L2(D3) power saving mode
Note: This bit is valid when set Bit1 to ‘1’.
Hardware Default value: 0x0
1
XCVR Function Enable
Enable the output of GPIO6 as “XCVR” function to shutdown external Serial Port transceiver in L2
power state.
1: Enable XCVR function output to GPIO6
0: Disable XCVR output to GPIO6, the GPIO6 is a generic GPIO function
Hardware Default value:
0: In LB mode
1: Others
2
Serial Port 1 System Clock Disable
1: Disabled Serial Port 1 system clock
0: Enabled Serial Port 1 system clock
Hardware Default value:
1: In LB mode
0: Others
3
Serial Port 2 System Clock Disable
1: Disabled Serial Port 2 system clock
0: Enabled Serial Port 2 system clock
Hardware Default value:
1: In LB mode
0: Others
4
Serial Port 3 System Clock Disable
1: Disabled Serial Port 3 system clock
0: Enabled Serial Port 3 system clock