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AX99100
ASIX AX99100 User Manual
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48
AX
99100
PCIe to Multi I/O Controller
Copyright ©
20
16
ASIX Electro
nics Corporation. All rights r
eserved.
EEPROM offset
CHIP_M
ODE = 011 (
4S
)
PCIe Function No.
0x48
00
0x49
00
0x4A
00
0x4B
00
0x4C
00
0x4D
00
0x4E
00
0x4F
00
0x50
00
0x51
00
0x52
00
0x53
01
0x54
00
0x55
7A
0x56
00
0x57
E4
0x58
00
0x59
00
0x5A
00
0x5B
A2
47
49
Table of Contents
Default Chapter
4
Table of Contents
4
1 Introduction
6
General Description
6
Ax99100 Block Diagram
7
Figure 1-1: Ax99100 Blockd
7
Iagram
7
Ax99100 Pinout Diagram
8
Figure 1-2: Ax99100 Pinoutd
8
Iagram
8
Signal Description
9
Table 1-1: Common Pin Description
9
Escription
9
Table 1-2: Pcie Pin Description
10
Table 1-3: Power /Ground Pind
10
GPIO and Mode Setting
11
Pin Description
11
Table 1-4: Gpio and Mode Setting
11
Serial Interface for COM Port
12
Com Port Pin Description
12
Serial Interface for Multi-Protocol Transceiver
13
In Description
13
Table 1-6: Serial Interface for Table 1-7: Serial Interface for
13
Serial Port with GPIO Enabled
14
Multi -Protocol Transceiver Pgpio Enabled Pin Description
14
Serial Port with Function Disabled
15
Description
15
Table 1-8: Serial Interface with
15
Parallel Port
16
Table 1-9: Parallel Port Pind
16
Escription
16
SPI Interface
17
Table 1-10: Spi Pin Description
17
Local Bus Interface
18
Escription
18
Table
18
2 Function Description
19
Clocks/Resets and Power
19
Pcie Operation
19
I 2 C Controller
21
Serial Port (Sp)
21
Parallel Port (Pp)
21
Spi Master Controller (Spi)
22
Local Bus Controller (Lb)
23
Gpio Function
24
Power Management
24
3 Chip Configuration
25
Boot Strapping Pins for Chip Mode
25
Table 3-1: Chip Mode Selection
25
Pins
25
Dtr Boot Strapping Pins for Serial Port
26
Table 3-2: Chip Mode Selection
26
Table 3-3: Dtr Mode Selection
26
Pins
26
Hardware Configuration Eeprom
27
Configuration EEPROM Memory Map for None Local Bus Interface
28
Bus Mode
28
Table 3-4: Configuration
28
Configuration EEPROM Memory Map for Local Bus Interface
34
Table 3-5: Configuration
34
Hardware Default Values Summary
43
Disable Unused Pcie Function in HWCFGEE
46
Table 3-7: the Hwchgee
46
Alues in each Chip_Mode Setting Content for 1S Setting
46
Pcie Configuration Space Map
49
4 Electrical Specifications
51
DC Characteristics
51
Absolute Maximum Ratings
51
Recommended Operating Condition
51
Leakage Current and Capacitance
51
DC Characteristics of 3.3V with 5V Tolerant I/O Pins
52
DC Characteristics of Voltage Regulator
52
Pcie Specifications
53
Power Consumption
54
Power-Up/Down and Power Management Sequence
55
Ac Timing Characteristics
56
Pcie Reference Clock Timing
56
C Timing
56
Table 4-1: I 2 C Master Controller
56
Serial Port Timing
57
Figure 4-1: Txd1 and Rxd1 T
57
SPI Timing
58
Figure 4-2: High Speed Spi Master
58
Local Bus Timing
59
Figure 4-3: Non - Multiplexed Bus
59
Figure 4-4: Isa-Like Bus Type with
60
Figure 4-5: Non - Multiplexedb
61
Figure 4-6: Multiplexedb
62
Iagram
62
Figure 4-7: Non - Multiplexed Bus
63
Figure 4-8: Isa-Like Bus Type with
64
Figure 4-9: Non - Multiplexedb
65
Figure 4-10: Multiplexedb
66
Iagram
66
Table 4-2: Local Bus Timingt
67
5 Package Information
68
7 Revision History
69
6 Ordering Information
69
4
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ASIX AX99100 Specifications
General
Brand
ASIX
Model
AX99100
Category
Controller
Language
English
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