ASIX AX99100 - Page 5

5
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
7 REVISION HISTORY................................................................................................................................ 69
List of Figures
FIGURE 1-1: AX99100 BLOCK DIAGRAM ................................................................................................................ 7
FIGURE 1-2: AX99100 PINOUT DIAGRAM ............................................................................................................... 8
FIGURE 4-1: TXD1 AND RXD1 TIMING DIAGRAM ................................................................................................ 57
FIGURE 4-2: HIGH SPEED SPI MASTER CONTROLLER TIMING DIAGRAM AND TABLE ........................................... 58
FIGURE 4-3: NON-MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................... 59
FIGURE 4-4: ISA-LIKE BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................................... 60
FIGURE 4-5: NON-MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM ............................. 61
FIGURE 4-6: MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM .................................................. 62
FIGURE 4-7: NON-MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................... 63
FIGURE 4-8: ISA-LIKE BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................................... 64
FIGURE 4-9: NON-MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM ............................. 65
FIGURE 4-10: MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ................................................ 66
List of Tables
TABLE 1-1: COMMON PIN DESCRIPTION .................................................................................................................. 9
TABLE 1-2: PCIE PIN DESCRIPTION ....................................................................................................................... 10
TABLE 1-3: POWER/GROUND PIN DESCRIPTION..................................................................................................... 10
TABLE 1-4: GPIO AND MODE SETTING PIN DESCRIPTION ..................................................................................... 11
TABLE 1-5: SERIAL INTERFACE FOR COM PORT PIN DESCRIPTION ....................................................................... 12
TABLE 1-6: SERIAL INTERFACE FOR MULTI-PROTOCOL TRANSCEIVER PIN DESCRIPTION ..................................... 13
TABLE 1-7: SERIAL INTERFACE FOR GPIO ENABLED PIN DESCRIPTION ................................................................ 14
TABLE 1-8: SERIAL INTERFACE WITH PORT2 AND PORT4 DISABLED PIN DESCRIPTION ......................................... 15
TABLE 1-9: PARALLEL PORT PIN DESCRIPTION ..................................................................................................... 16
TABLE 1-10: SPI PIN DESCRIPTION ........................................................................................................................ 17
TABLE 1-11: LOCAL BUS PIN DESCRIPTION ........................................................................................................... 18
TABLE 3-1: CHIP MODE SELECTION PINS .............................................................................................................. 25
TABLE 3-2: CHIP MODE SELECTION TABLE ........................................................................................................... 26
TABLE 3-3: DTR MODE SELECTION PINS ............................................................................................................... 26
TABLE 3-4: CONFIGURATION EEPROM MEMORY MAP FOR NONE LOCAL BUS MODE .......................................... 28
TABLE 3-5: CONFIGURATION EEPROM MEMORY MAP FOR LOCAL BUS .............................................................. 34
TABLE 3-6: HARDWARE DEFAULT VALUES IN EACH CHIP_MODE SETTING ....................................................... 43
TABLE 3-7: THE HWCHGEE CONTENT FOR 1S SETTING ....................................................................................... 46
TABLE 4-1: I
2
C MASTER CONTROLLER TIMING TABLE.......................................................................................... 56
TABLE 4-2: LOCAL BUS TIMING TABLE ................................................................................................................. 67