71
ATtiny26(L)
1477G–AVR–03/05
Writing a logical one to this bit forces a change in the Compare Match output pin PB3
(OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and
COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force
Output Compare bit can be used to change the output pin value regardless of the timer
value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a
compare match had occurred, but no interrupt is generated. The FOC1B bit always
reads as zero. FOC1B is not in use if PWM1B bit is set.
• Bit 1 – PWM1A: Pulse Width Modulator A Enable
When set (one) this bit enables PWM mode based on comparator OCR1A in
Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a
compare match with OCR1C Register value.
• Bit 0 – PWM1B: Pulse Width Modulator B Enable
When set (one) this bit enables PWM mode based on comparator OCR1B in
Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a
compare match with OCR1C Register value.
Timer/Counter1 Control
Register B – TCCR1B
• Bit 7 – CTC1: Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock
cycle after a compare match with OCR1C Register value. If the control bit is cleared,
Timer/Counter1 continues counting and is unaffected by a compare match.
• Bit 6 – PSR1: Prescaler Reset Timer/Counter1
When this bit is set (one), the Timer/Counter prescaler will be reset. The bit will be
cleared by hardware after the operation is performed. Writing a zero to this bit will have
no effect. This bit will always read as zero.
• Bit 5..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Bit 7 6 5 4 3 2 1 0
$2F ($4F) CTC1 PSR1 – – CS13 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
To Next Page
Loading...
Need help?
General
