Ayecka SR1 - Application CPU; ASI

Advanced DVB-S2 Receiver - Operational Manual
SR1 Hardware
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2.3 Application CPU
The SR1 supports an option for the Application CPU. The Application CPU is a daughter board
that can be added to the SR1.
The Application CPU has a GigE interface to the internal switch.
The CPU can be selected according to the application requirement.
For additional information please contact info@ayecka.com.
2.4 ASI
The SR1 supports an option for single ASI input and ASI output.
The ASI interfaces are connected directly to the FPGA that process all the Transport streams
and GigE traffic.
The ASI interface is optional.
For additional information please contact info@ayecka.com..