Compal JHL90 - 7. Power Interface Details; 7.1 Power requirement; 7.2 Power;EE Interface definition

JHL90 Service Manual
7. Power interface
7.1 Power requirement
Load
Voltage
Item Description
Min. Max. Peak Normal
Ripple /
Noise
Tolerance
Control
signal
Remark
1 +CPU_CORE
0 40A
By VID
control
CPU spec. CPU spec. VR_ON
2 +0.9VS
0 0.75A 0.9V 5% SUSP
3 +1.05VS
0 3A 1.05V 5% SUSP
4 +1.5VS
0 6A 1.5V 5% SYSON
5 +1.8V
0 3A 1.8V 5% SYSON
6 +3VS
0 0.3A 3V 5%: SUSP
7 +3VALW
0 5A 3V 5%
8 +5VALW
0 5A 5V 5%
*1
*1: Always on when AC exist no AC exist control by EC_ON
7.2 Power/EE Interface definition:
Voltage Rails
Power Plane Description S1 S3 S5
VIN Adapter Power supply (19V) N/A N/A N/A
B+ AC or battery Power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
SIGNAL
STATE
SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S3 (Suspend to RAM) LOW HGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
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