176 D50 PLC User's Manual
High Speed Counter
The D50 PLC provides two 24-bit, 10kHz high-speed counters (on the DC-input units only). Each of
the two counters functions identically to the other. Each has a set of 7 registers allocated for its
configuration and operation, plus an additional comparision register that they share. High-speed
counter channel 0 uses registers R4 to R10, while channel 1 uses register R19 to R25. Register R26 is
a shared comparison register that is used by both channels. The purpose of each register is described
in greater detail below.
Register Descriptions
MODE (R004, R019)
The mode register is used to turn on the high-speed counter, configure which mode it will be operating
in, and enable or disable the inputs used by the counter. Each bit in the low byte of the MODE register
is used to turn On or Off a feature of the high-speed counter channel.
STR (R005/6, R020/21)
The STR registers are a pair of registers that the user places the START value for the counter channel
into. When the register is configured for Ring Count Mode, or when the counter is reset using the
Preset bit or the Preset input, the START value is loaded into the present value of the counter. Since
the counter is a 24-bit value, two registers are required – the first holds the low 16 bits of the value,
and the second holds the high 8 bits.
END (R007/8, R022/23)
The END registers are a pair of registers that hold the Set Value for the high-speed counter. When the
present value is counting, bits are set in the comparison register that indicate when the counter is
below, at, or above the END value (see FLAG below). The END value is also a 24-bit value requiring
two registers, and is set by the user.
PV (R009/10, R024/25)
The PV registers are a pair of registers that hold the Present Value for the high-speed counter. The PV
registers hold the actual counting value of the inputs coming into the PLC. Like STR and END, PV is
a 24-bit value.
FLAG (R026)
The FLAG register provides comparison bits between the high-speed counter Present Values (PV) and
End Values (END). Each counter channel has three bits in the FLAG register that indicate whether the
PV is greater than (>), less than (<), or equal to (=) the END value. Since the equal to comparison is a
latched bit, a fourth bit is provided to reset the = bit.
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