DIGITAL-LOGIC MICROSPACE PCC-P5

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DIGITAL-LOGIC AG PCCP5 Manual V2.3

4.6 BIOS

4.6.1 ROM-BIOS Sockets

An EPROM socket with 8 Bit wide data access normally contains the board's AT compatible ROM-BIOS. The

socket takes any of a 27C010 to 29F010 EPROM (or equivalent) device. The board's wait-state control logic

automatically inserts four memory wait states in all CPU accesses to this socket. The ROM-BIOS sockets

occupies the memory area from C0000H through FFFFFh; however, the board's ASIC logic reserves the en-

tire area from C0000h through FFFFFh for onboard devices, so this area is already usable for ROM-DOS

and BIOS expansion modules. Consult the appropriate address map for the MICROSPACE PCC-P5 ROM-

BIOS sockets.

4.6.1.1 Standard BIOS FLASH 29F010

DEVICE: 29F010 PLCC32 with 90ns access time

MAP: E0000 - FFFFFh Chipset BIOS from AMI including the SCSI BIOS

4.6.1.2 VGA BIOS FLASH 29F010

DEVICE: 29F010 PLCC32 with 90ns access time

( with 29F020 are 4 BIOS Segments with 64k jumper selectable)

Segment-MAP: C0000 - CBFFF VGA BIOS 32k or 44k

DIGITAL-LOGIC MICROSPACE PCC-P5 - 4.6 BIOS