ControlWave Instruction Manual (CI-ControlWave)
Revised Nov-2010 Installation 2-29
To ensure that the “Receive Data” lines are in a proper state during
inactive transmission periods, you must maintain certain bias voltage
levels at the master and most distant slave units (end nodes). These end
nodes also require the insertion of 100Ω terminating resistors to
properly balance the network.
You must also configure secondary communication board switches at
each node to establish proper network performance. Accomplish this by
configuring switches listed so that the 100Ω termination resistors and
biasing networks are installed at the end nodes and are removed at all
other nodes on the network. You enable receiver biasing and
termination using SCB switch SW1 (for COM3) and SCB switch SW2
(for COM4). See Table 2-4 in Section 2.4.1 Setting DIP Switches on the
CPU Modules for information on RS-485 termination and loopback
control switch settings.
2.4.4 Connections to Ethernet Port(s) on the CPU Module
The ControlWave can support from one to three Ethernet ports. These
use a 10/100Base-T RJ-45 modular connector that provides a shielded
twisted pair interface to an Ethernet hub. Two LEDs per port provide
transmit and receive status indications:
Table 2-13 shows port assignments for the Ethernet ports.
Table 2-13. Ethernet Ports
Connector Name Function Notes
J4 on CPU
board
Ethernet Port 1 8-pin RJ-45 (RS-485) – Shielded Twisted
Pair 10/100Base-T
J5 on SCB
board
Ethernet Port 2 8-pin RJ-45 (RS-485) – Shielded Twisted
Pair 10/100Base-T
Requires SCB board
J6 on SCB
board
Ethernet Port 3 8-pin RJ-45 (RS-485) – Shielded Twisted
Pair 10/100Base-T
Requires SCB board
A typical Ethernet hub provides eight 10/100Base-T RJ-45 ports (with
port 8 having the capability to link either to another hub or to an
Ethernet communications port). Both ends of the Ethernet twisted pair
cable are equipped with modular RJ-45 connectors.
18
Looking into
receptacle
Figure 2-16. RJ-45 Ethernet Connector
These cables have a one-to-one wiring configuration as shown in Figure
2-17. Table 2-14 provides the assignment and definitions of the 8-pin
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