Signal Name Sign. Pairs Differential Single- I/O Bank
ended
IO_B64_<...> 4 0 - In/Out 64 (HP)
1
IO_B65_<...> 20 10 In/Out In/Out 65 (HP)
1
IO_B66_<...> 50 24 In/Out In/Out 66 (HP)
1
IO_BN_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 46 (HD)
1
for ZU4/ZU5
47 (HD)
1
for ZU7
Refer to Section 2.9.3 for details.
IO_BO_<...> 24 12 In/Out (no LVDS/LVPECL outputs
supported; internal differential ter-
mination not supported)
In/Out 45 (HD)
1
for ZU4/ZU5
48 (HD)
1
for ZU7
Refer to Section 2.9.3 for details.
Total 122 58 - - -
Table 5: User I/Os
The multi-gigabit transceiver (MGT) are described in section 2.10.
2.9.2 I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination
with certain Mercury boards they may have a specific role).
PCIe Reset Signal (PERST#)
Table 6 lists the I/O pin exceptions on the Mercury+ XU8 SoC module related to the PCIe reset connection.
I/O Name Module Connector Pin Description
PS_MIO42_PERST# A-104 When the pin has a low value, its value is routed via a
1 kΩ resistor to ETH0_TXD3_PERST# pin (MIO30) and
via a 47 kΩ resistor to PL_PERST# (MPSoC package
pin AF2) for PCIe PERST# connection implementation
Table 6: I/O Pin Exceptions - PERST#
When the Mercury+ XU8 SoC module is used in combination with a Mercury+ PE1 base board as a PCIe
device, the PERST# signal coming from the PCIe edge connector on the module connector pin A-104
(PS_MIO42_PERST#) is driven further to PL_PERST# and to ETH0_TXD3_PERST# (MIO30) when its value is low.
When a PCIe block on the PL side is used, the PERST# signal is connected to the MPSoC pin PL_PERST# via
a 47 kΩ resistor.
When a PCIe block on the PS side is used, the PERST# signal is routed via a 1 kΩ resistor to MIO30. This is
the default MIO pin used for the reset signal of the PCIe PS built-in block, therefore it was chosen for the
reset implementation. The Ethernet controller 0 is disabled when the PCIe hard block is used; note that any
1
HD = high density pins, HP = high performance pins; Refer to the Zynq UltraScale+ MPSoC Overview [22] for details.
D-0000-454-001 18 / 60 Version 06, 18.11.2019
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