2.13 Reset
The power-on reset signal (POR) and the PS system reset signal (SRST) of the MPSoC device are available
on the module connector.
Pulling PS_POR# low resets the MPSoC device, the Ethernet and the USB PHYs, and the QSPI and eMMC
flash devices. Please refer to the Enclustra Module Pin Connection Guidelines [10] for general rules regarding
the connection of reset pins.
Pulling PS_SRST# low resets the MPSoC device and enables the connection between QSPI flash and module
connector, allowing the flash to be programmed from an external SPI master.
For details on the functions of the PS_POR_B and PS_SRST_B signals refer to the Zynq UltraScale+ MPSoC
Technical Reference Manual [18].
Table 21 presents the available reset signals. Both signals, PS_POR# and PS_SRST#, have on-board 10 kΩ
pull-up resistors to VCC_CFG_MIO. For on-board devices using 1.8 V signaling, a PS_POR# low voltage variant
is generated (PS_POR#_LV).
Signal Name Connector Pin Package Pin FPGA Pin Type Description
PS_POR# A-132 N19 PS_POR_B Power-on reset
PS_SRST# A-124 P20 PS_SRST_B System reset
Table 21: Reset Resources
Please note that PS_POR# is automatically asserted if PWR_GOOD is low.
2.14 LEDs
There are three active-low user LEDs on the Mercury+ XU8 SoC module - two of them are connected to the
PS and one connected to the PL.
Signal Signal Remarks
Name Location
PS_LED0# A18 (MIO24) User function/active-low
PS_LED1# B18 (MIO25) User function/active-low
PL_LED2# AF13 User function/active-low
Table 22: User LEDs
In addition to the user LEDs, two status LEDs are equipped on the module, offering details on the configu-
ration process for debugging purposes.
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