2.18.2 Signal Description
The eMMC flash signals are connected to the MIO pins 13-22 for 8-bit data transfer mode. The command
signal has a 4.7 kΩ pull-up resistor to 1.8 V and the data lines have 47 kΩ pull-up resistors to 1.8 V.
2.19 SD Card
An SD card can be connected to the PS MIO pins 45-51. The corresponding MIO pins are available on the
module connector. Information on SD card boot mode is available in Section 3.9.
Please note that external pull-ups are needed for SD card operation. Depending on the selected voltage for
VCC_CFG_MIO, a level shifter to 3.3 V may be required (some level shifters also have built-in pull-ups).
For booting from an Ultra High Speed (UHS) SD card, an SD 3.0 compliant level shifter is required on the
base board and VCC_CFG_MIO must be set to 1.8 V. Please note that this boot mode has not been tested,
but it may be supported in the future.
2.20 Dual Gigabit Ethernet
Two 10/100/1000 Mbit Ethernet PHYs are available on the Mercury+ XU8 SoC module, both connected to
the PS via RGMII interfaces.
2.20.1 Ethernet PHY Type
Table 30 describes the equipped Ethernet PHY devices type on the Mercury+ XU8 SoC module.
PHY Type Manufacturer Type
KSZ9031RNX Microchip (Micrel) 10/100/1000 Mbit
Table 30: Gigabit Ethernet PHYs Type
2.20.2 Signal Description
PHY 0 is connected to ETH 0 controller from the PS I/O bank 501. One of the Ethernet TX data signals is
shared with the PCIe reset signal (PERST#); if the application requires a hard PCIe block, the ETH 0 interface
is not available. Refer to Section 2.9.2 for details on the PERST# connection.
Warning!
Gigabit Ethernet 0 interface is not available when the PCIe endpoint in the PS is used (because of the
PERST# connection).
PHY 1 is connected to ETH 3 controller from the PS bank 502. The corresponding MIO signals (64-75) are
shared between Ethernet PHY 1 and USB PHY 1, therefore only one of them can be used. By default the
Ethernet connection is enabled.
Warning!
Gigabit Ethernet 1 interface is not available when USB 1 interface is active.
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