Pin Signal Value Description
MODE[3-0] 1110 RGMII mode: advertise all capabilities (10/100/1000, half/full duplex) ex-
cept 1000Base-T half duplex.
PHYAD[2-0]
011 PHY0: MDIO address 3
111 PHY1: MDIO address 7
Clk125_EN 0 125 MHz clock output disabled
LED_MODE 1 Single LED mode
LED1/LED2 1 Active-low LEDs
Table 32: Gigabit Ethernet PHYs Configuration - Bootstraps
For the Ethernet PHY configuration via the MDIO interface, the MDC clock frequency must not exceed 2
MHz.
2.20.6 RGMII Delays Configuration
The two Ethernet PHYs are connected directly to hard MAC controllers present in the MPSoC device. In
order to achieve the best sampling eye for the RX and TX data, it is recommended to adjust the pad skew
delays as specified in Table 33. These values have been successfully tested on Enclustra side.
The delays can be adjusted by programming the RGMII pad skew registers of the Ethernet PHY; please refer
to the PHY datasheet for details.
PHY Register Name Register Value [binary] Delay Value
RXD0-RXD3 0111 0 ps
RX_DV 0111 0 ps
RX_CLK 01111 0 ps
TXD0-TXD3 0111 0 ps
TX_EN 0111 0 ps
GTX_CLK 11110 900 ps
Table 33: Gigabit Ethernet PHYs Configuration - RGMII Delays
2.21 USB 2.0
Two USB 2.0 PHYs are available on the Mercury+ XU8 SoC module, both connected to the PS to I/O bank
502. USB PHY 0 can be configured as host or device and USB PHY 1 can be used only as host.
2.21.1 USB PHY Type
Table 34 describes the equipped USB PHYs device type on the Mercury+ XU8 SoC module.
D-0000-454-001 41 / 60 Version 06, 18.11.2019
To Next Page
Loading...
Need help?
General
