The naming convention for the GTH MGT I/Os is:
MGT_B<BANK_LETTER>_<FUNCTION>_<P
ACKAGE_PIN>_<POLARITY>.
For example, MGT_BB_TX2_L3_N is located on pin L3 of MGT I/O bank B, it is a transmit pin and it has neg-
ative polarity.
Signal Name Signal Description Pairs I/O Bank
MGT_BA_RX<...> MGT receivers 4
223 for ZU4/ZU5, 224 for ZU7
MGT_BA_TX<...> MGT transmitters 4
MGT_BA_REFCLK<...> MGT reference input clocks 2
MGT_BB_RX<...> MGT receivers 4
224 for ZU4/ZU5, 225 for ZU7
MGT_BB_TX<...> MGT transmitters 4
MGT_BB_REFCLK<...> MGT reference input clocks 2
MGT_BC_RX<...> MGT receivers 4
225 for ZU4/ZU5, 226 for ZU7
MGT_BC_TX<...> MGT transmitters 4
MGT_BC_REFCLK<...> MGT reference input clocks 2
MGT_BD_RX<...> MGT receivers 4
226 for ZU4/ZU5, 227 for ZU7
MGT_BD_TX<...> MGT transmitters 4
MGT_BD_REFCLK<...> MGT reference input clocks 2
Total 40
Table 12: MGT Pairs
Twelve of the GTH pairs and six corresponding clocks are routed to module connector C, while four GTH
pairs and two reference input clock differential pairs are routed to module connector B.
The GTH MGTs on the MPSoC device support data rates of 12.5 Gbit/sec on speedgrade 1 devices and of
16.375 Gbit/sec on the other devices. Note that the maximum bandwidth is limited to 15 Gbit/sec by the
module connector.
The MPSoC devices equipped on the Mercury+ XU8 SoC module can support up to two integrated PCIe
Gen3 ×16 interfaces on the PL side, implemented using GTH transceivers. Simultaneous usage of these
interfaces is limited to the available hardware resources (number of transceivers and lane mapping).
Warning!
It is recommended to use redrivers on the base board for PCIe Gen3 or other high-speed interfaces
implementations, and to perform channel simulation.
GTR Transceivers
There are four GTR MGT pairs and two reference input clock differential pairs on the Mercury+ XU8 SoC
module connected to I/O bank 505; these are routed to module connector B.
D-0000-454-001 25 / 60 Version 06, 18.11.2019
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