Warning!
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is
released from reset. Violating this rule may damage the equipped MPSoC device, as well as other
devices on the Mercury+ XU8 SoC module.
3.2 Module Connector C Detection
Signal C_PRSNT# (pin C-167) is equipped with a 4.7 kΩ pull-up resistor to 3.3 V on the module. Since the
VCC_IO pins on connector C are not used, C_PRSNT# does not influence the behavior of the module.
For compatibility with other Enclustra modules, it is recommended to connect C_PRSNT# to GND on the
base board if the designed base board has three connectors.
3.3 Pull-Up During Configuration
The Pull-Up During Configuration signal (PUDC) is pulled to GND on the module; as PUDC is an active-low
signal, all FPGA I/Os will have the internal pull-up resistors enabled during device configuration.
If the application requires the pull-up during configuration to be disabled, this can be achieved by removing
R222 component and by mounting R221 - in this configuration the PUDC pin is connected to 1.8 V.
Figure 12 illustrates the configuration of the I/O signals during power-up. Figure 13 indicates the location of
the pull-up/pull-down resistors on the module PCB - lower right part on the bottom view drawing.
Figure 12: Pull-Up During Configuration (PUDC) and Power-on Reset Delay Override (PORSEL)
D-0000-454-001 45 / 60 Version 06, 18.11.2019
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