Signal Name Module Connector Pin PS Dedicated Pin Resistor
JTAG_TCK A-123 PS_JTAG_TCK 10 kΩ pull-up to VCC_CFG_MIO
JTAG_TMS A-119 PS_JTAG_TMS 10 kΩ pull-up to VCC_CFG_MIO
JTAG_TDI A-117 PS_JTAG_TDI 10 kΩ pull-up to VCC_CFG_MIO
JTAG_TDO A-121 PS_JTAG_TDO 10 kΩ pull-up to VCC_CFG_MIO
Table 38: JTAG Interface - PL and PS Access and Debug
3.6.2 External Connectivity
JTAG signals can be connected directly on the base board to a JTAG connector. No pull-up/pull-down re-
sistors are necessary. The VREF pin of the programmer must be connected to VCC_CFG_MIO.
It is recommended to add 22 Ω series termination resistors between the module and the JTAG header, close
to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface.
3.6.3 JTAG Boot Mode
Starting with revision 2, support for JTAG boot mode has been added to increase the usability of the module
with Xilinx tools, for example for QSPI flash programming or FPGA bitstream loading.
The following steps are required in order to boot the module in JTAG mode:
• Set the boot mode selection signals for QSPI boot
• Short-circuit R252 (see Figure 14) while powering-up the module (in order to sample the MPSoC boot
selection pins correctly for JTAG boot mode)
Figure 14: JTAG Boot Mode Resistor - Assembly Drawing Top View (lower right part) for Revision 2 Modules
D-0000-454-001 48 / 60 Version 06, 18.11.2019
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