Voltage Voltage Rated Voltage Shut down Influences
Supply Name Value Current Source via PWR_EN PWR_GOOD
VCC_INT 0.72 V/0.85 V/0.9 V
(PL core supply)
35 A VCC_MOD Yes Yes
VCC_PSINT 0.85 V/0.9 V (PS core supply) 6 A VCC_MOD Yes Yes
VCC_0V85
6
0.85 V
(GTR transceiver supply)
0.5 A VCC_1V2 Yes No
VCC_0V9 0.9 V 6 A VCC_MOD Yes Yes
VCC_1V2 1.2 V 6 A VCC_MOD Yes Yes
VCC_BAT_FPGA 1.2 V 10 mA VCC_BAT No No
VCC_1V8 1.8 V 3 A VCC_MOD Yes Yes
VCC_2V5 2.5 V 0.5 A VCC_3V3 Yes
7
No
VCC_3V3 3.3 V 6 A VCC_MOD No Yes
VCC_5V0 5.0 V 0.15 A VCC_MOD No No
Table 13: Generated Power Supplies
6 7
In the standard configuration the PL core supply is 0.85 V. For custom configurations, in which a speedgrade
-3E MPSoC device is equipped, an assembly option is available to switch the PL core operating voltage to 0.9
V. Similarly, in situations in which a speedgrade -2LE or -1LI device is used, an assembly option is available
to switch the PL core operating voltage to 0.72 V.
In the standard configuration the PS core supply is 0.85 V. For custom configurations, in which a speedgrade
-3E MPSoC device is equipped, an assembly option is available to switch the PS core operating voltage to
0.9 V.
Please refer to the Enclustra Module Pin Connection Guidelines for general rules on the power pins [10].
The power consumption of the video codec unit (VCU) on the VCC_INT_VCU rail is limited to 4 A. This issue
will be fixed starting with revision 3.
Power Converter Synchronization
All switching DC/DC converters used on the Mercury+ XU8 SoC module support synchronization of the
switching frequency with an external clock. The module includes a power synchronization circuit, which
may drive a clock generated by the MPSoC device to all the DC/DC converters.
By default, the free-running switching frequency of the DC/DC converters is set. To set the switching fre-
quency to a desired value, a clock must be generated on MPSoC pin W9 of bank 66. Table 14 presents the
6
An LDO is used to generate the GTR transceiver supply, when a -1LI, -2LE, or -3E speedgrade MPSoC device is used. For the other
speedgrades, VCC_INT is used.
7
Please note that on modules revision 1.1 the 2.5 V supply is not powered off by the PWR_EN signal. If this voltage is used to supply
VCC_IO pins, power sequencing on the base board is required.
D-0000-454-001 27 / 60 Version 06, 18.11.2019
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