MINI-LINKEandEMicro
Table 2 Priority for RMX switching in the receiver
RMX Switch switching
criteria (receiver)
Alarm Priority
Switching due to hardware failure
Manual switch mode
1
MMU does not exist NCC Ra
2
CSS fail MMU Proc. Hardware
Proc. Software
EEPROM
3
RAU Proc. Hardware
Proc. Software
EEPROM
RCC
RX High priority 1 Demod Clock BB1, 2
Radio ID
BER 10
–3
(fixed)
RX Frequency
4
RX High priority 2 Radio Frame
5
Hitless switching (error free) due to fading
FEC A detected error w ill activate
switching (with no Hitless Phase
Alarm)
6
Low
RF level
AGC
Threshold but no Hitless
Ph
ase Alarm
7
RMX switching is accomplished by FIFO buffers and a fast switch. The delay in
the buffer is controlled so that the data phase differences in the radio sections
(due to cables etc. are compensated. See also Section 8.5.1 on page 143 for
restrictions on cable lengths in 1+1 configurations.
The switch is placed before the linecoder in the Radio Frame Multiplexer (RMX).
The switch command is synchronized to the bit timing.
Alar m information from the receiving side is collected in the Control and
Supervision processor in each MMU and sent to the Switch Logic unit in the
SMU.
Alar m generation has a certain delay, not critical for fading switching which is
hitless because fading means slow traffic degradation.
The control signals f rom the Switch Logic control the traffic routing of the radio
composite signal between the two MMUs.
60
AE/LZT 110 2012 R8C 2002-03-04
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