45
Service Manual
2-22
comprised of dual retriggerable monostable multivibrator A2U5, NAND gates from
A2U6, diode A2CR3, and various resistive and capacitive timing components.
At power-up, capacitor A2C3 begins to charge up through resistor A2R3. The voltage
level on A2C3 is detected by an input of Schmitt-Trigger NAND gate A2U6-12. The
output of this gate (A2U6-11) then drives the active high reset signal (RESET) to the rest
of the system. When the voltage on A2C3 is below the input threshold of A2U6-12,
A2U6-11 is high. As soon as A2C3 charges up to the threshold of A2U6-12, A2U6-11
goes low. The RESET signal drives NAND gate inputs A2U6-1 and A2U6-2, to generate
the active low reset signal (RESET*) at A2U6-3.
When the RESET signal transitions from high to low (A2U5-1), the Watchdog Timer is
triggered initially, causing A2U5-13 to go high. This half of the dual retriggerable
monostable multivibrator uses timing components A2R2 and A2C2 to define a nominal
4.75-second watchdog timeout period. Each time a low-to-high transition of DISTX is
detected on A2U5-2, capacitor A2C2 is discharged to restart the timeout period. If there
are no low-to-high transitions on DISTX during the 4.75-second period, A2U5-13
transitions from high to low, triggers the other half of A2U5, and causes output A2U5-12
to go low. A2U5-12 is then inverted by A2U6 to drive the RESET signal high, causing a
system reset. The low duration of A2U5-12 is determined by timing components A2Z1
and A2C4 and is nominally 460 µs. When A2U5-12 goes high again, RESET goes low to
retrigger the Watchdog Timer.
2-47. Display Controller with FIP
The Display Controller is a 4-bit, single-chip microcomputer with high-voltage outputs
that drive a vacuum-fluorescent display directly. The controller receives commands over
a three-wire communication channel from the Microprocessor on the Main Assembly.
Each command is transferred serially to the Display Controller on the display transmit
(DISTX) signal, with bits being clocked into the Display Controller on the rising edges
of the display clock signal (DSCLK). Responses from the Display Controller are sent to
the Microprocessor on the display receive signal (DISRX) and are clocked out of the
Display Controller on the falling edge of DSCLK.
Figure 2-9 shows the waveforms during a single command byte transfer. Note that a high
DISRX signal is used to hold off further transfers until the Display Controller has
processed the previously received byte of the command.
Once reset, the Display Controller performs a series of self-tests, initializing display
memory and holding the DISRX signal high. After DISRX goes low, the Display
Controller is ready for communication; on the first command byte from the
Microprocessor, the Display Controller responds with a self-test results response. If all
self-tests pass, a response of 00000001 (binary) is returned. If any self-test fails, a
response of 01010101 (binary) is returned. The Display Controller initializes its display
memory to one of four display patterns depending on the states of the DTEST* (A2U1-
41) and LTE* (A2U1-13) inputs. The DTEST* input is pulled up by A2Z1, but may be
pulled down by jumpering A2TP4 to A2TP3 (GND). The LTE* input is pulled down by
A2R12, but may be pulled up by jumpering A2TP5 to A2TP6 (VCC). The default
conditions of DTEST* and LTE* cause the Display Controller to turn all segments on
bright at power-up.
Table 2-6 defines the logic and the selection process for the four display initialization
modes.
The two display test patterns are a mixture of on and off segments forming a
recognizable pattern that allows for simple testing of display operation. The Display
Controller provides 10 grid control outputs and 14 anode control outputs. Each of these
24 high-voltage outputs provides an active driver to the +5 V dc supply and a passive 70
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