Diagnostic Testing and Troubleshooting
Display Assembly Troubleshooting
5
5-17
Chip Enable is present, the problem is with either the RAM itself or the address, data,
RD*, or WR* lines between the 6303Y Main Processor and the external RAM.
Figure 5-3 shows the timing relationships of the 6303Y Main Processor lines LIR* and
WR* to the system clock (E) and the address lines A0..A15. The ROM and RAM Chip
Enables correspond to the active (low) region shown for the address lines.
5-15. Display Assembly Troubleshooting
The following discussion is helpful if it has been determined that the Display Assembly
is faulty. This initial determination may not be arrived at easily, since an improperly
operating display may be the result of a hardware or software problem that is not a direct
functional part of the Display Assembly. Consult the General Troubleshooting
Procedures found earlier in this chapter for procedures to isolate the fault to the Display
Assembly. Use the following discussion of display software operation when
troubleshooting problems within a known faulty Display Assembly. A Display Extender
Cable is available (PN 867952) for use during troubleshooting.
Figure 5-4 shows the timing of communications between the main processor and the
display controller.
The Display Controller reads the DTEST* and LTE* inputs to determine how to
initialize the display memory. DTEST* and LTE* default to logic 1 and logic 0,
respectively, to cause all display segments to be initialized to "on". DTEST* is
connected to test points A2TP4, and LTE* is connected to A2TP5. Either test point can
be jumpered to VCC (A2TP6) or GND (A2TP3) to select other display initialization
patterns. Display Test Patterns #1 and #2 are a mixture of "on" and "off" segments with a
recognizable pattern to aid in troubleshooting problems involving individual display
segments. When either of the special display patterns is selected, the beeper is also
sounded for testing without interaction with the main processor. Table 5-5 indicates the
display initialization possibilities. Figures 5-5 and 5-6 show grid and anode assignments
for primary and secondary displays, respectively.
BIT 7 BIT 6
DSCLK
Clear to receive
DISTX
DISRX
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Clear to receive
35
qb09.eps
Figure 5-4. Display Controller to Microprocessor Signals
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