GE P54C - Protection Reoperation and Evolving Fault Logic Diagram; Fault Memory Logic Diagram; Autoreclose in Progress; Figure 67: Protection Reoperation and Evolving Fault Logic Diagram (Module 20)

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5.7.4 PROTECTION REOPERATION AND EVOLVING FAULT LOGIC DIAGRAM

V03331

TARANY

TMEMANY

Prot ReOp

LastShot

Set CB1 CL

1P DTime

Seq Counter = 1

A/R Lockout

CB Closed 3 ph

CB ARIP

Prot ReOp

Evolve Lock

Evolve 3Ph

CB Failed AR

0.02

Discrim Time

0.02

Figure 67: Protection Reoperation and Evolving Fault logic diagram (Module 20)

5.7.5 FAULT MEMORY LOGIC DIAGRAM

V03320

RESPRMEM

Trip Inputs A

Ext Fault APh

FLTMEM 2P

FLTMEM 3P

AR Start

Trip Inputs B

Trip Inputs C

Ext Fault BPh

Ext Fault CPh

Figure 68: Fault Memory logic diagram (Module 15)

5.8 AUTORECLOSE IN PROGRESS

The AR In Progress module produces various signals to indicate to other modules and functions that an

Autor

eclose operation is currently in progress.

Chapter 7 - Autoreclose P54A/B/C/E

156 P54xMED-TM-EN-1

Main Page

Default Chapter3
- Table of Contents3
Chapter 1 Introduction27
- Circuit Breaker Fail Logic - Part28
- Rear Serial Port28
Chapter Overview29
- Trip Circuit Supervision Scheme29
- Cip29
Foreword30
- Target Audience30
- Typographical Conventions30
- Cip30
- Nomenclature31
- Compliance31
- Cip31
Product Scope32
- Ordering Options32
- Cip32
Features and Functions33
- Current Differential Protection Functions33
- Protection Functions33
- Control Functions33
- Measurement Functions34
- Communication Functions34
Logic Diagrams35
- Figure 1: Key to Logic Diagrams36
Functional Overview37
- Figure 2: Functional Overview37
Chapter 2 Safety Information39
Chapter Overview41
Health and Safety42
Symbols43
Installation, Commissioning and Servicing44
- Lifting Hazards44
- Electrical Hazards44
- UL/CSA/CUL Requirements45
- Fusing Requirements45
- Equipment Connections46
- Protection Class 1 Equipment Requirements46
- Pre-Energisation Checklist47
- Peripheral Circuitry47
- Upgrading/Servicing48
Decommissioning and Disposal49
Regulatory Compliance50
- EMC Compliance: 2014/30/EU50
- LVD Compliance: 2014/35/EU50
- R&TTE Compliance: 2014/53/EU50
- UL/CUL Compliance50
- ATEX Compliance: 2014/34/EU50
Chapter 3 Hardware Design53
Chapter Overview55
Hardware Architecture56
- Coprocessor Hardware Architecture56
- Figure 3: Hardware Architecture56
- Figure 4: Coprocessor Hardware Architecture57
Mechanical Implementation58
- Housing Variants58
- Figure 5: Exploded View of IED58
- List of Boards59
Front Panel61
- Front Panel Compartments61
- Figure 6: Front Panel (60TE)61
- Keypad62
- Front Serial Port (SK1)62
- Front Parallel Port (SK2)63
- Fixed Function Leds63
- Function Keys63
- Programable Leds64
Rear Panel65
- Figure 7: Rear View of Populated Case65
- Figure 8: Terminal Block Types66
Boards and Modules67
- Pcbs67
- Subassemblies67
- Figure 9: Rear Connection to Terminal Block67
- Main Processor Board68
- Figure 10: Main Processor Board68
- Power Supply Board69
- Figure 11: Power Supply Board69
- Figure 12: Power Supply Assembly70
- Watchdog71
- Figure 13: Power Supply Terminals71
- Rear Serial Port72
- Figure 14: Watchdog Contact Terminals72
- Input Module - 1 Transformer Board73
- Figure 15: Rear Serial Port Terminals73
- Figure 16: Input Module - 1 Transformer Board73
- Input Module Circuit Description74
- Figure 17: Input Module Schematic74
- Transformer Board75
- Figure 18: Transformer Board75
- Input Board76
- Figure 19: Input Board76
- Standard Output Relay Board77
- Figure 20: Standard Output Relay Board - 8 Contacts77
- IRIG-B Board78
- Figure 21: IRIG-B Board78
- Fibre Optic Board79
- Figure 22: Fibre Optic Board79
- Rear Communication Board80
- Ethernet Board80
- Figure 23: Rear Communication Board80
- Figure 24: Ethernet Board80
- Redundant Ethernet Board82
- Figure 25: Redundant Ethernet Board82
- Coprocessor Board84
- Current Differential Inputs84
- Coprocessor Board with 1PPS Input84
- Figure 26: Fully Populated Coprocessor Board84
Chapter 4 Software Design87
Chapter Overview89
Sofware Design Overview90
- Figure 27: Software Architecture90
System Level Software91
- Real Time Operating System91
- System Services Software91
- Self-Diagnostic Software91
- Startup Self-Testing91
- System Boot91
- System Level Software Initialisation92
- Platform Software Initialisation and Monitoring92
- Continuous Self-Testing92
Platform Software94
- Record Logging94
- Settings Database94
- Interfaces94
Protection and Control Functions95
- Acquisition of Samples95
- Frequency Tracking95
- Direct Use of Sample Values95
- System Level Software Initialisation95
- Fourier Signal Processing96
- Programmable Scheme Logic97
- Event Recording97
- Figure 28: Frequency Response (Indicative Only)97
- Disturbance Recorder98
- Fault Locator98
- Function Key Interface98
Chapter 5 Configuration99
Chapter Overview101
Settings Application Software102
Using the HMI Panel103
- Navigating the HMI Panel104
- Getting Started104
- Figure 29: Navigating the HMI104
- Default Display105
- Default Display Navigation106
- Figure 30: Default Display Navigation106
- Password Entry107
- Processing Alarms and Records107
- Menu Structure108
- Changing the Settings109
- Direct Access (the Hotkey Menu)110
- Setting Group Selection Using Hotkeys110
- Control Inputs110
- Circuit Breaker Control111
- Function Keys111
Line Parameters113
- Tripping Mode113
- CB Trip Conversion Logic Diagram113
- Figure 31: Circuit Breaker Trip Conversion Logic Diagram (Module 63)113
- Residual Compensation114
- Mutual Compensation114
Date and Time Configuration116
- Using an SNTP Signal116
- Using an IRIG-B Signal116
- Using an IEEE 1588 PTP Signal116
- Without a Timing Source Signal117
- Time Zone Compensation117
- Daylight Saving Time Compensation118
Settings Group Selection119
Chapter 6 Current Differential Protection121
Chapter Overview123
Current Differential Protection Principle124
- Numerical Current Differential Protection124
- Multi-Ended Line Differential Protection125
- Basic Principles and Algorithm Design for Multi-Ended Differential Protection125
- Fault Discrimination125
- Differential Characteristics126
- Figure 32: Sample Multi-Ended System126
- Figure 33: Current Differential Discriminative Criterion127
- Basic Algorithm128
- Features of Multi-Ended Line Differential128
- Algorithm Overview128
- Communication Requirements129
- Figure 34: Overall Scheme Designed for Multi-Ended Differential Protection129
Charging Current Compensation130
- Figure 35: Two-Ended Transmission Line130
Synchronisation of Current Signals132
- Time Alignment Using Ping-Pong Technique132
- Figure 36: Ping-Pong Measurement for Alignment of Current Signals132
- Remote Terminal Time Alignment133
- Time Delay Interpolation134
- Figure 37: Snapshot of Available Data for Processing at each Terminal134
CT Saturation135
- Figure 38: CT Saturation Technique135
- Figure 39: Original Current Waveforms136
- Figure 40: Ipos and Ineg Current Waveforms137
- Figure 41: Internal External Fault Binary137
CT Compensation138
- Figure 42: CT Compensation138
Current Differential Intertripping139
- Figure 43: Permissive Intertripping Example139
Stub Bus Differential Protection140
- Figure 44: Stub Bus Protection140
Application Notes141
- Multi-End Current Differential Protection141
- Figure 45: Six Terminal, Four Junction Topology and Ring Structure141
- Figure 46: Six Terminal Ring Structure with Channel Allocation141
- Feeder Topology142
- Configuring the Feeder Topology142
- Figure 47: Six Terminal, Four Junction Topology142
- Line Parameter Data143
- Configuring the Protection Communications144
- Setting up the Phase Differential Characteristic145
- Sensitivity under Heavy Loads145
- Permissive Intertripping147
- CT Ratio Correction Setting Guidelines147
- Feeders with Small Tapped Loads148
Chapter 7 Autoreclose149
Chapter Overview151
Introduction to Autoreclose152
Autoreclose Implementation153
- Autoreclose Logic Inputs from External Sources154
- Circuit Breaker Healthy Input154
- Inhibit Autoreclose Input154
- Block Autoreclose Input154
- Reset Lockout Input155
- Pole Discrepancy Input155
- External Trip Indication155
- Autoreclose Logic Inputs155
- Trip Initiation Signals155
- Circuit Breaker Status Inputs155
- System Check Signals155
- Autoreclose Logic Outputs155
- Autoreclose Operating Sequence156
- AR Timing Sequence - Transient Fault156
- AR Timing Sequence - Evolving/Permanent Fault156
- Figure 48: Autoreclose Sequence for a Transient Fault156
- AR Timing Sequence - Evolving/Permanent Fault Single-Phase157
- Figure 49: Autoreclose Sequence for an Evolving or Permanent Fault157
- Figure 50: Autoreclose Sequence for an Evolving or Permanent Fault - Single-Phase Operation157
Autoreclose System Map158
- Figure 51: Key to Logic Diagrams159
- Autoreclose System Map Diagrams160
- Figure 52: Autoreclose System Map - Part 1160
- Figure 53: Autoreclose System Map - Part 2161
- Figure 54: Autoreclose System Map - Part 3162
- Figure 55: Autoreclose System Map - Part 4163
- Figure 56: Autoreclose System Map - Part 5164
- Autoreclose Internal Signals165
- Autoreclose DDB Signals167
Logic Modules173
- Circuit Breaker Status Monitor173
- CB State Monitor Logic Diagram174
- Figure 57: CB State Monitor Logic Diagram (Module 1)174
- Circuit Breaker Open Logic175
- Circuit Breaker Open Logic Diagram175
- Circuit Breaker in Service Logic175
- Circuit Breaker in Service Logic Diagram175
- Figure 58: Circuit Breaker Open Logic Diagram (Module 3)175
- Figure 59: CB in Service Logic Diagram (Module 4)175
- Autoreclose OK Logic Diagram176
- Autoreclose Enable176
- Autoreclose Enable Logic Diagram176
- Autoreclose Modes176
- Figure 60: Autoreclose OK Logic Diagram (Module 8)176
- Figure 61: Autoreclose Enable Logic Diagram (Module 5)176
- Single-Phase and Three-Phase Autoreclose177
- Autoreclose Modes Enable Logic Diagram178
- AR Force Three-Phase Trip Logic178
- AR Force Three-Phase Trip Logic Diagram178
- Autoreclose Initiation Logic178
- Figure 62: Autoreclose Modes Enable Logic Diagram (Module 9)178
- Figure 63: Force Three-Phase Trip Logic Diagram (Module 10)178
- Autoreclose Initiation Logic Diagram180
- Autoreclose Trip Test Logic Diagram180
- Figure 64: Autoreclose Initiation Logic Diagram (Module 11)180
- Figure 65: Autoreclose Trip Test Logic Diagram (Module 12)180
- AR External Trip Initiation Logic Diagram181
- Figure 66: Autoreclose Initiation by External Trip or Evolving Conditions (Module 13)181
- Protection Reoperation and Evolving Fault Logic Diagram182
- Fault Memory Logic Diagram182
- Autoreclose in Progress182
- Figure 67: Protection Reoperation and Evolving Fault Logic Diagram (Module 20)182
- Figure 68: Fault Memory Logic Diagram (Module 15)182
- Autoreclose in Progress Logic Diagram183
- Sequence Counter183
- Figure 69: Autoreclose in Progress Logic Diagram (Module 16)183
- Autoreclose Sequence Counter Logic Diagram184
- Autoreclose Cycle Selection184
- Single-Phase Autoreclose Cycle Selection Logic Diagram184
- Figure 70: Autoreclose Sequence Counter Logic Diagram (Module 18)184
- Figure 71: Single-Phase Autoreclose Cycle Selection Logic Diagram (Module 19)184
- 3-Phase Autoreclose Cycle Selection185
- Dead Time Control185
- Figure 72: Three-Phase Autoreclose Cycle Selection Logic Diagram (Module 21)185
- Dead Time Start Enable Logic Diagram186
- Figure 73: Dead Time Start Enable Logic Diagram (Module 22)186
- 1-Phase Dead Time Logic Diagram187
- Figure 74: Single-Phase Dead Time Logic Diagram (Module 24)187
- 3-Phase Dead Time Logic Diagram188
- Circuit Breaker Autoclose188
- Figure 75: Three-Phase Dead Time Logic Diagram (Module 25)188
- Circuit Breaker Autoclose Logic Diagram189
- Reclaim Time189
- Figure 76: Circuit Breaker Autoclose Logic Diagram (Module 32)189
- Prepare Reclaim Initiation Logic Diagram190
- Reclaim Time Logic Diagram190
- Figure 77: Prepare Reclaim Initiation Logic Diagram (Module 34)190
- Figure 78: Reclaim Time Logic Diagram (Module 35)190
- Succesful Autoreclose Signals Logic Diagram191
- Autoreclose Reset Successful Indication Logic Diagram191
- CB Healthy and System Check Timers191
- Figure 79: Successful Autoreclose Signals Logic Diagram (Module 36)191
- Figure 80: Autoreclose Reset Successful Indication Logic Diagram (Module 37)191
- CB Healthy and System Check Timers Logic Diagram192
- Autoreclose Shot Counters192
- Figure 81: Circuit Breaker Healthy and System Check Timers Healthy Logic Diagram (Module 39)192
- Autoreclose Shot Counters Logic Diagram193
- Figure 82: Autoreclose Shot Counters Logic Diagram (Module 41)193
- Circuit Breaker Control194
- CB Control Logic Diagram194
- Figure 83: CB Control Logic Diagram (Module 43)194
- Circuit Breaker Trip Time Monitoring195
- CB Trip Time Monitoring Logic Diagram195
- Autoreclose Lockout195
- Figure 84: Circuit Breaker Trip Time Monitoring Logic Diagram (Module 53)195
- CB Lockout Logic Diagram196
- Figure 85: AR Lockout Logic Diagram (Module 55)196
- Reset Circuit Breaker Lockout197
- Reset CB Lockout Logic Diagram197
- Figure 86: Reset Circuit Breaker Lockout Logic Diagram (Module 57)197
- Pole Discrepancy198
- Pole Discrepancy Logic Diagram198
- Circuit Breaker Trip Conversion198
- Figure 87: Pole Discrepancy Logic Diagram (Module 62)198
- CB Trip Conversion Logic Diagram199
- Monitor Checks for CB Closure199
- Figure 88: Circuit Breaker Trip Conversion Logic Diagram (Module 63)199
- Check Synchronisation Monitor for CB Closure200
- Figure 89: Check Synchronisation Monitor for CB Closure (Module 60)200
- Voltage Monitor for CB Closure201
- Synchronisation Checks for CB Closure201
- Figure 90: Voltage Monitor for CB Closure (Module 59)201
- Three-Phase Autoreclose System Check Logic Diagram203
- Figure 91: Three-Phase Autoreclose System Check Logic Diagram (Module 45)203
- CB Manual Close System Check Logic Diagram204
- Figure 92: CB Manual Close System Check Logic Diagram (Module 51)204
Setting Guidelines205
- De-Ionising Time Guidance205
- Dead Timer Setting Guidelines205
- Example Dead Time Calculation205
- Reclaim Time Setting Guidelines206
Chapter 8 CB Fail Protection207
Chapter Overview209
Circuit Breaker Fail Protection210
Circuit Breaker Fail Implementation211
- Circuit Breaker Fail Timers211
- Zero Crossing Detection211
Circuit Breaker Fail Logic213
- Circuit Breaker Fail Logic - Part213
- Figure 96: Circuit Breaker Fail Logic - Part213
- Circuit Breaker Fail Logic - Part214
- Circuit Breaker Fail Logic - Part 3215
- Figure 93: Circuit Breaker Fail Logic - Part216
- Figure 94: Circuit Breaker Fail Logic - Part216
- Figure 95: Circuit Breaker Fail Logic - Part216
Application Notes217
- Reset Mechanisms for CB Fail Timers217
- Setting Guidelines (CB Fail Timer)217
- Setting Guidelines (Undercurrent)218
- Figure 97: CB Fail Timing218
Chapter 9 Current Protection Functions219
Chapter Overview221
Phase Fault Overcurrent Protection222
- POC Implementation222
- Directional Element222
- POC Logic224
- Figure 98: Phase Overcurrent Protection Logic Diagram224
Negative Sequence Overcurrent Protection225
- Negative Sequence Overcurrent Protection Implementation225
- Directional Element225
- NPSOC Logic226
- Application Notes226
- Setting Guidelines (Current Threshold)226
- Setting Guidelines (Time Delay)226
- Figure 99: Negative Phase Sequence Overcurrent Protection Logic Diagram226
- Setting Guidelines (Directional Element)227
Earth Fault Protection228
- Earth Fault Protection Implementation228
- IDG Curve228
- Directional Element229
- Residual Voltage Polarisation229
- Figure 100: IDG Characteristic229
- Negative Sequence Polarisation230
- Earth Fault Protection Logic231
- Application Notes231
- Residual Voltage Polarisation Setting Guidelines231
- Setting Guidelines (Directional Element)231
- Figure 101: Earth Fault Protection Logic Diagram231
Sensitive Earth Fault Protection233
- SEF Protection Implementation233
- EPATR B Curve233
- Sensitive Earth Fault Protection Logic234
- Figure 102: EPATR B Characteristic Shown for TMS = 1.0234
- Figure 103: Sensitive Earth Fault Protection Logic Diagram234
- Application Notes235
- Insulated Systems235
- Figure 104: Current Distribution in an Insulated System with C Phase Fault235
- Setting Guidelines (Insulated Systems)236
- Figure 105: Phasor Diagrams for Insulated System with C Phase Fault236
- Figure 106: Positioning of Core Balance Current Transformers237
High Impedance REF238
- High Impedance REF Principle238
- Figure 107: High Impedance REF Principle238
- Figure 108: High Impedance REF Connection239
Thermal Overload Protection240
- Single Time Constant Characteristic240
- Dual Time Constant Characteristic240
- Thermal Overload Protection Implementation241
- Thermal Overload Protection Logic241
- Application Notes241
- Setting Guidelines for Dual Time Constant Characteristic241
- Figure 109: Thermal Overload Protection Logic Diagram241
- Figure 110: Spreadsheet Calculation for Dual Time Constant Thermal Characteristic242
- Figure 111: Dual Time Constant Thermal Characteristic242
- Setting Guidelines for Single Time Constant Characteristic243
Broken Conductor Protection245
- Broken Conductor Protection Implementation245
- Broken Conductor Protection Logic245
- Application Notes245
- Setting Guidelines245
- Figure 112: Broken Conductor Logic245
Chapter 10 Voltage Protection Functions247
Chapter Overview249
Undervoltage Protection250
- Undervoltage Protection Implementation250
- Undervoltage Protection Logic251
- Figure 113: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)251
- Application Notes252
- Undervoltage Setting Guidelines252
Overvoltage Protection253
- Overvoltage Protection Implementation253
- Overvoltage Protection Logic254
- Figure 114: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)254
- Application Notes255
- Overvoltage Setting Guidelines255
Compensated Overvoltage256
Residual Overvoltage Protection257
- Residual Overvoltage Protection Implementation257
- Residual Overvoltage Logic258
- Application Notes258
- Calculation for Solidly Earthed Systems258
- Figure 115: Residual Overvoltage Logic258
- Calculation for Impedance Earthed Systems259
- Figure 116: Residual Voltage for a Solidly Earthed System259
- Setting Guidelines260
- Figure 117: Residual Voltage for an Impedance Earthed System260
Chapter 11 Frequency Protection Functions261
Chapter Overview263
Frequency Protection264
- Underfrequency Protection264
- Underfrequency Protection Implementation264
- Underfrequency Protection Logic265
- Application Notes265
- Overfrequency Protection265
- Overfrequency Protection Implementation265
- Figure 118: Underfrequency Logic (Single Stage)265
- Overfrequency Protection Logic266
- Application Notes266
- Figure 119: Overfrequency Logic (Single Stage)266
Independent R.O.C.O.F Protection267
- Indepenent R.O.C.O.F Protection Implementation267
- Independent R.O.C.O.F Protection Logic267
- Figure 120: Rate of Change of Frequency Logic (Single Stage)267
Chapter 12 Monitoring and Control269
Chapter Overview271
Event Records272
- Event Types272
- Opto-Input Events273
- Contact Events273
- Alarm Events273
- Fault Record Events274
- Maintenance Events274
- Protection Events274
- Figure 121: Fault Recorder Stop Conditions274
- Security Events275
- Platform Events275
Disturbance Recorder276
Measurements277
- Measured Quantities277
- Measurement Setup277
- Fault Locator277
- Opto-Input Time Stamping277
CB Condition Monitoring278
- Broken Current Accumulator279
- CB Trip Counter279
- Figure 122: Broken Current Accumulator Logic Diagram279
- Figure 123: CB Trip Counter Logic Diagram279
- CB Operating Time Accumulator280
- Excessive Fault Frequency Counter280
- Figure 124: Operating Time Accumulator280
- Figure 125: Excessive Fault Frequency Logic Diagram280
- Reset Lockout Alarm281
- Figure 126: Reset Lockout Alarm Logic Diagram281
- CB Condition Monitoring Logic282
- Reset Circuit Breaker Lockout282
- Figure 127: CB Condition Monitoring Logic Diagram282
- Reset CB Lockout Logic Diagram283
- Application Notes283
- Setting the Thresholds for the Total Broken Current283
- Figure 128: Reset Circuit Breaker Lockout Logic Diagram (Module 57)283
- Setting the Thresholds for the Number of Operations284
- Setting the Thresholds for the Operating Time284
- Setting the Thresholds for Excesssive Fault Frequency284
CB State Monitoring285
- CB State Monitor Logic Diagram286
- Figure 129: CB State Monitor Logic Diagram (Module 1)286
Circuit Breaker Control287
- CB Control Using the IED Menu287
- CB Control Using the Hotkeys288
- CB Control Using the Function Keys288
- Figure 130: Hotkey Menu Navigation288
- CB Control Using the Opto-Inputs289
- Remote CB Control289
- Figure 131: Default Function Key PSL289
- CB Healthy Check290
- Synchronisation Check290
- CB Control AR Implications290
- Figure 132: Remote Control of Circuit Breaker290
- CB Control Logic Diagram291
- Figure 133: CB Control Logic Diagram (Module 43)291
Pole Dead Function292
- Pole Dead Logic292
- Figure 134: Pole Dead Logic292
System Checks293
- System Checks Implementation293
- VT Connections293
- Voltage Monitoring294
- Check Synchronisation294
- Check Syncronisation Vector Diagram294
- Figure 135: Check Synchronisation Vector Diagram295
- Voltage Monitor for CB Closure296
  - Figure 136: Voltage Monitor for CB Closure (Module 59)296
  - System Checks296
- Check Synchronisation Monitor for CB Closure297
- Figure 137: Check Synchronisation Monitor for CB Closure (Module 60)297
- System Check PSL298
- Application Notes298
- Predictive Closure of Circuit Breaker298
- Voltage and Phase Angle Correction298
- Figure 138: System Check PSL298
Chapter 13 Supervision301
Chapter Overview303
Current Differential Supervision304
- Current Differential Starter Supervision304
- Current Differential Starter Supervision Logic306
- Figure 139: Current Differential Starter Supervision Logic306
- Current Differential Start Logic307
- Switched Communication Path Supervision307
- Figure 140: Current Differential Function Start Logic307
- Communications Asymmetry Supervision308
- Figure 141: Switched Communication Path Supervision308
- Figure 142: Communication Asymmetry Supervision309
Voltage Transformer Supervision310
- Loss of One or Two Phase Voltages310
- Loss of All Three Phase Voltages310
- Absence of All Three Phase Voltages on Line Energisation310
- VTS Implementation311
- VTS Logic313
- Figure 143: VTS Logic314
Current Transformer Supervision315
- Differential CTS315
- Differential CTS Logic316
- CTS Implementation316
- Figure 144: Differential CTS316
- Standard CTS Logic317
- CTS Blocking317
- Application Notes317
- Setting Guidelines317
- Figure 145: Standard CTS317
- Differential CTS Setting Guidelines318
Trip Circuit Supervision319
- Trip Circuit Supervision Scheme319
- Resistor Values319
- Psl for Tcs Scheme 1320
- Trip Circuit Supervision Scheme 2320
- Figure 146: TCS Scheme321
- Figure 147: PSL for TCS Scheme321
- Figure 148: TCS Scheme321
- Figure 149: PSL for TCS Scheme 2321
- Figure 150: TCS Scheme 3322
- Figure 151: PSL for TCS Scheme 3322
Chapter 14 Digital I/O and PSL Configuration323
Chapter Overview325
Configuring Digital Inputs and Outputs326
Scheme Logic327
- Figure 152: Scheme Logic Interfaces327
- PSL Editor328
- PSL Schemes328
- PSL Scheme Version Control328
Configuring the Opto-Inputs329
Assigning the Output Relays330
Fixed Function Leds331
- Trip LED Logic331
- Figure 153: Trip LED Logic331
Configuring Programmable Leds332
Function Keys334
Control Inputs335
Chapter 15 Fibre Teleprotection337
Chapter Overview339
Fibre Teleprotection Implementation340
- Communication Setup340
- Protection Communications Channel341
- Protection Comms Message Slot Allocation for each Protection Scheme341
- Figure 154: Fibre Teleprotection Connections for a Six-Terminal Scheme341
- Figure 155: Two Terminal Single Channel Scheme341
- Figure 156: Two Terminal Dual Channel Scheme342
- Figure 157: Three Terminal Scheme342
- Figure 158: Four Terminal Scheme343
- Figure 159: Five Terminal Scheme344
- Error Handling for Protection Communications345
- Figure 160: Six Terminal Scheme345
- Fibre Teleprotection Scheme Terminal Addressing346
- Physical Connection346
- Direct Connection347
- Indirect Connection347
Communications Supervision348
IM64 Logic349
- Figure 161: IM64 Channel Fail and Scheme Fail Logic349
- Figure 162: IM64 General Alarm Signals Logic349
- Figure 163: IM64 Communications Mode and IEEE C37.94 Alarm Signals350
Application Notes351
- Scheme Reconfiguration351
- Alarm Management351
- Alarm Logic351
- Two-Ended Scheme Extended Supervision352
- Three-Ended Scheme Extended Supervision353
- Figure 164: IM64 Two-Terminal Scheme Extended Supervision353
- Figure 165: IM64 Three-Terminal Scheme Extended Supervision353
Chapter 16 Electrical Teleprotection355
Chapter Overview357
Introduction358
Teleprotection Scheme Principles359
- Direct Tripping359
- Permissive Tripping359
Implementation360
Configuration361
- Figure 166: Example Assignment of Intermicom Signals Within the PSL362
Connecting to Electrical Intermicom363
- Short Distance363
- Long Distance363
- Figure 167: Direct Connection363
- Figure 168: Indirect Connection Using Modems363
Application Notes364
Chapter 17 Communications367
Chapter Overview369
Communication Interfaces370
Serial Communication371
- EIA(RS)232 Bus371
- EIA(RS)485 Bus371
- EIA(RS)485 Biasing Requirements372
- K-Bus372
- Figure 169: RS485 Biasing Circuit372
- Figure 170: Remote Communication Using K-Bus373
Standard Ethernet Communication374
- Hot-Standby Ethernet Failover374
Redundant Ethernet Communication375
- Supported Protocols375
- Parallel Redundancy Protocol376
- Figure 171: IED Attached to Separate Lans376
- High-Availability Seamless Redundancy (HSR)377
- HSR Multicast Topology377
- Figure 172: HSR Multicast Topology377
- HSR Unicast Topology378
- HSR Application in the Substation378
- Figure 173: HSR Unicast Topology378
- Rapid Spanning Tree Protocol379
- Figure 174: HSR Application in the Substation379
- Figure 175: IED Attached to Redundant Ethernet Star or Ring Circuit379
- Self Healing Protocol380
- Figure 176: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities380
- Figure 177: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches380
- Dual Homing Protocol381
- Figure 178: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches381
- Figure 179: Dual Homing Mechanism382
- Configuring IP Addresses383
- Figure 180: Application of Dual Homing Star at Substation Level383
- Configuring the IED IP Address384
- Configuring the REB IP Address384
- Figure 181: IED and REB IP Address Configuration384
- PRP/HSR Configurator387
- Connecting the IED to a PC387
- Installing the Configurator388
- Starting the Configurator388
- Figure 182: Connection Using (A) an Ethernet Switch and (B) a Media Converter388
- PRP/HSR Device Identification389
- Selecting the Device Mode389
- PRP/HSR IP Address Configuration389
- SNTP IP Address Configuration389
- Check for Connected Equipment389
- PRP Configuration389
- HSR Configuration390
- Filtering Database390
- End of Session391
- RSTP Configurator391
- Connecting the IED to a PC391
- Installing the Configurator392
- Starting the Configurator392
- RSTP Device Identification392
- Figure 183: Connection Using (A) an Ethernet Switch and (B) a Media Converter392
- RSTP IP Address Configuration393
- SNTP IP Address Configuration393
- Check for Connected Equipment393
- RSTP Configuration393
- End of Session394
- Switch Manager394
- Installation395
- Setup396
- Network Setup396
- Bandwidth Used396
- Reset Counters396
- Check for Connected Equipment396
- Mirroring Function397
- Ports On/Off397
- Vlan397
- End of Session397
Simple Network Management Protocol (SNMP)398
- SNMP Management Information Bases398
- Main Processor MIBS Structure398
- Redundant Ethernet Board MIB Structure399
- Accessing the MIB403
- Main Processor SNMP Configuration403
Data Protocols405
- Courier405
- Physical Connection and Link Layer405
- Courier Database406
- Settings Categories406
- Setting Changes406
- Event Extraction406
- Disturbance Record Extraction408
- Programmable Scheme Logic Settings408
- Time Synchronisation408
- Courier Configuration409
- Physical Connection and Link Layer410
- Iec 60870-5-103410
- Initialisation411
- Time Synchronisation411
- Spontaneous Events411
- General Interrogation (GI)411
- Cyclic Measurements411
- Commands411
- Test Mode412
- Disturbance Records412
- Command/Monitor Blocking412
- IEC 60870-5-103 Configuration412
- Dnp413
- Physical Connection and Link Layer414
- Object 1 Binary Inputs414
- Object 10 Binary Outputs414
- Object 20 Binary Counters415
- Object 30 Analogue Input415
- Figure 184: Control Input Behaviour415
- Object 40 Analogue Output416
- Object 50 Time Synchronisation416
- DNP3 Device Profile416
- DNP3 Configuration424
- Iec 61850425
- Benefits of IEC 61850426
- IEC 61850 Interoperability426
- The IEC 61850 Data Model426
- IEC 61850 in Micom Ieds427
- Figure 185: Data Model Layers in IEC61850427
- IEC 61850 Data Model Implementation428
- IEC 61850 Communication Services Implementation428
- IEC 61850 Peer-To-Peer (GOOSE) Communications428
- Mapping GOOSE Messages to Virtual Inputs428
- Ethernet Functionality429
- IEC 61850 Configuration429
- Iec 61850 Edition 2430
- Figure 186: Edition 2 System - Backward Compatibility431
- Figure 187: Edition 1 System - Forward Compatibility Issues431
- Figure 188: Example of Standby IED432
- Figure 189: Standby IED Activation Process433
Read Only Mode434
- Courier Protocol Blocking434
- IEC 61850 Protocol Blocking435
- Read-Only Settings435
- Read-Only DDB Signals435
Time Synchronisation436
- Demodulated IRIG-B436
- Figure 190: GPS Satellite Timing Signal436
- IRIG-B Implementation437
- Sntp437
- Loss of SNTP Server Signal Alarm437
- IEEE 1588 Precision Time Protocol437
- Accuracy and Delay Calculation437
- PTP Domains438
- Time Synchronsiation Using the Communication Protocols438
- Figure 191: Timing Error Using Ring or Line Topology438
Chapter 18 Cyber-Security439
Overview441
The Need for Cyber-Security442
Standards443
- NERC Compliance443
- Cip 002444
- Cip 007445
- Ieee 1686-2007445
Cyber-Security Implementation447
- NERC-Compliant Display447
- Four-Level Access448
- Figure 192: Default Display Navigation448
- Blank Passwords449
- Password Rules449
- Access Level Ddbs450
- Enhanced Password Security450
- Password Strengthening450
- Password Validation450
- Password Blocking451
- Password Recovery452
- Password Encryption453
- Disabling Physical Ports453
- Disabling Logical Ports453
- Security Events Management454
- Logging out456
Chapter 19 Installation457
Chapter Overview459
Handling the Goods460
- Receipt of the Goods460
- Unpacking the Goods460
- Storing the Goods460
- Dismantling the Goods460
Mounting the Device461
- Flush Panel Mounting461
- Figure 193: Location of Battery Isolation Strip461
- Rack Mounting462
- Figure 194: Rack Mounting of Products462
Cables and Connectors464
- Terminal Blocks464
- Figure 195: Terminal Block Types464
- Power Supply Connections465
- Earth Connnection465
- Current Transformers465
- Voltage Transformer Connections466
- Watchdog Connections466
- EIA(RS)485 and K-Bus Connections466
- IRIG-B Connection466
- Opto-Input Connections466
- Output Relay Connections466
- Ethernet Metallic Connections467
- Ethernet Fibre Connections467
- RS232 Connection467
- Download/Monitor Port467
- GPS Fibre Connection467
- Fibre Communication Connections467
Case Dimensions468
- Case Dimensions 40TE468
- Figure 196: 40TE Case Dimensions468
- Case Dimensions 60TE469
- Figure 197: 60TE Case Dimensions469
- Case Dimensions 80TE470
- Figure 198: 80TE Case Dimensions470
Chapter 20 Commissioning Instructions471
Chapter Overview473
General Guidelines474
Commissioning Test Menu475
- Opto I/P Status Cell (Opto-Input Status)475
- Relay O/P Status Cell (Relay Output Status)475
- Test Port Status Cell475
- Monitor Bit 1 to 8 Cells475
- Test Mode Cell476
- Test Pattern Cell476
- Contact Test Cell476
- Test Leds Cell476
- Test Autoreclose Cell476
- Static Test Mode477
- Loopback Mode477
- IM64 Test Pattern478
- IM64 Test Mode478
- Red and Green LED Status Cells478
- Using a Monitor Port Test Box478
Commissioning Equipment479
- Recommended Commissioning Equipment479
- Essential Commissioning Equipment479
- Advisory Test Equipment480
Product Checks481
- Product Checks with the IED De-Energised481
- Visual Inspection482
- Current Transformer Shorting Contacts482
- Insulation482
- External Wiring482
- Watchdog Contacts483
- Power Supply483
- Product Checks with the IED Energised483
- Test LCD484
- Date and Time484
- Test Leds485
- Test Alarm and Out-Of-Service Leds485
- Test Trip LED485
- Test User-Programmable Leds485
- Test Opto-Inputs485
- Test Output Relays485
- Test Serial Communication Port RP1486
- Figure 199: RP1 Physical Connection486
- Test Serial Communication Port RP2487
- Figure 200: Remote Communication Using K-Bus487
- Test Ethernet Communication488
- Secondary Injection Tests488
- Test Current Inputs488
- Test Voltage Inputs488
Electrical Intermicom Communication Loopback490
- Setting up the Loopback490
- Loopback Test490
- Figure 201: Intermicom Loopback Testing490
- Intermicom Command Bits491
- Intermicom Channel Diagnostics491
- Simulating a Channel Failure491
Intermicom 64 Communication492
- Checking the Interface492
- Setting up the Loopback492
- Loopback Test493
Setting Checks494
- Apply Application-Specific Settings494
- Transferring Settings from a Settings File494
- Entering Settings Using the HMI494
IEC 61850 Edition 2 Testing496
- Using IEC 61850 Edition 2 Test Modes496
- IED Test Mode Behaviour496
- Sampled Value Test Mode Behaviour496
- Simulated Input Behaviour497
- Testing Examples497
- Figure 202: Simulated Input Behaviour497
- Test Procedure for Real Values498
- Test Procedure for Simulated Values - no Plant498
- Figure 203: Test Example 1498
- Test Procedure for Simulated Values - with Plant499
- Figure 204: Test Example 2499
- Contact Test500
- Figure 205: Test Example 3500
Current Differential Protection501
- Current Differential Bias Characteristic501
- Lower Slope501
- Figure 206: Current Differential Bias Characteristics501
- Upper Slope502
- Current Differential Operation and Contact Assignment502
Protection Timing Checks504
- Dependency Conditions504
- Overcurrent Check504
- Connecting the Test Circuit504
- Performing the Test505
- Check the Operating Time505
System Check and Check Synchronism506
- Check Synchronism Pass506
- Check Synchronism Fail506
Check Trip and Autoreclose Cycle507
End-To-End Communication Tests508
- Remove Local Loopbacks508
- Restoring Direct Fibre Connections508
- Restoring C37.94 Fibre Connections509
- Remove Remote Loopbacks509
- Verify Communication between Ieds509
Onload Checks510
- Confirm Voltage Connections510
- Confirm Current Connections510
- Measure Capacitive Charging Current511
- Check Differential Current511
- Check Current Transformer Polarity511
- On-Load Directional Test511
Final Checks512
Chapter 21 Maintenance and Troubleshooting513
Chapter Overview515
Maintenance516
- Maintenance Checks516
- Alarms516
- Opto-Isolators516
- Output Relays516
- Measurement Accuracy516
- Replacing the Device517
- Repairing the Device518
- Removing the Front Panel518
- Figure 207: Possible Terminal Block Types518
- Replacing Pcbs519
- Replacing the Main Processor Board519
- Replacement of Communications Boards520
- Figure 208: Front Panel Assembly520
- Replacement of the Input Module521
- Replacement of the Power Supply Board521
- Replacement of the I/O Boards522
- Recalibration522
- Changing the Battery522
- Post Modification Tests523
- Battery Disposal523
- Cleaning523
Troubleshooting524
- Self-Diagnostic Software524
- Power-Up Errors524
- Error Message or Code on Power-Up524
- Out of Service LED on at Power-Up525
- Error Code During Operation526
- Backup Battery526
- Mal-Operation During Testing526
- Failure of Output Contacts526
- Failure of Opto-Inputs526
- Incorrect Analogue Signals527
- Coprocessor Board Failures527
- Signalling Failure Alarm (on Its Own)527
- C Diff Failure Alarm (on Its Own)527
- Signalling Failure and C Diff Failure Alarms Together527
- Incompatible IED527
- Comms Changed527
- IEEE C37.94 Fail528
- PSL Editor Troubleshooting528
- Diagram Reconstruction528
- PSL Version Check528
- Repair and Modification Procedure528
Chapter 22 Technical Specifications531
Chapter Overview533
Interfaces534
- Front Serial Port534
- Download/Monitor Port534
- Rear Serial Port534
- Fibre Rear Serial Port534
- Optional Rear Serial Port (SK5)535
- IRIG-B (Demodulated)535
- IRIG-B (Modulated)535
- Rear Serial Port 2535
- Rear Ethernet Port Copper536
- Rear Ethernet Port Fibre536
- 100 Base Fx Receiver Characteristics536
- 100 Base Fx Transmitter Characteristics537
- PPS Port537
- Fibre Teleprotection Interface537
Protection Functions538
- Phase Current Differential Protection538
- Fibre Teleprotection Transfer Times538
- Autoreclose and Check Synychronism538
- Phase Overcurrent Protection538
- Phase Overcurrent Directional Parameters539
- Earth Fault Protection539
- Earth Fault Directional Parameters539
- Sensitive Earth Fault Protection540
- Sensitive Earth Fault Protection Directional Element540
- High Impedance Restricted Earth Fault Protection540
- Negative Sequence Overcurrent Protection541
- NPSOC Directional Parameters541
- Circuit Breaker Fail and Undercurrent Protection541
- Broken Conductor Protection541
- Thermal Overload Protection541
Monitoring, Control and Supervision542
- Voltage Transformer Supervision542
- Standard Current Transformer Supervision542
- Differential Current Transformer Supervision542
- CB State and Condition Monitoring542
- PSL Timers543
Measurements and Recording544
- General544
- Disturbance Records544
- Event, Fault and Maintenance Records544
- Fault Locator544
Ratings545
- AC Measuring Inputs545
- Current Transformer Inputs545
- Voltage Transformer Inputs545
- Auxiliary Supply Voltage545
- Nominal Burden546
- Power Supply Interruption546
- Battery Backup547
Input / Output Connections548
- Isolated Digital Inputs548
- Nominal Pickup and Reset Thresholds548
- Standard Output Contacts548
- High Break Output Contacts549
- Watchdog Contacts549
Mechanical Specifications550
- Physical Parameters550
- Enclosure Protection550
- Mechanical Robustness550
- Transit Packaging Performance550
Type Tests551
- Insulation551
- Creepage Distances and Clearances551
- High Voltage (Dielectric) Withstand551
- Impulse Voltage Withstand Test551
Environmental Conditions552
- Ambient Temperature Range552
- Temperature Endurance Test552
- Ambient Humidity Range552
- Corrosive Environments552
Electromagnetic Compatibility553
- Mhz Burst High Frequency Disturbance Test553
- Damped Oscillatory Test553
- Immunity to Electrostatic Discharge553
- Electrical Fast Transient or Burst Requirements553
- Surge Withstand Capability553
- Surge Immunity Test554
- Immunity to Radiated Electromagnetic Energy554
- Radiated Immunity from Digital Communications554
- Radiated Immunity from Digital Radio Telephones554
- Immunity to Conducted Disturbances Induced by Radio Frequency Fields554
- Magnetic Field Immunity555
- Conducted Emissions555
- Radiated Emissions555
- Power Frequency555
Regulatory Compliance556
- EMC Compliance: 2014/30/EU556
- LVD Compliance: 2014/35/EU556
- R&TTE Compliance: 2014/53/EU556
- UL/CUL Compliance556
- ATEX Compliance: 2014/34/EU556
Appendix A Ordering Options559
Appendix B Settings and Signals561

GE P54C - Protection Reoperation and Evolving Fault Logic Diagram; Fault Memory Logic Diagram; Autoreclose in Progress; Figure 67: Protection Reoperation and Evolving Fault Logic Diagram (Module 20)

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