Infineon Technologies TLE5012B - Page 95

TLE5012B
SSC Registers
User’s Manual 95 Rev. 1.2, 2018-02
HSM_PLP (multi-purpose) 8:5 w Hall Switch Mode: Pole-Pair Configuration
0000
B
1 pole pairs
0001
B
2 pole pairs
0010
B
3 pole pairs
...
B
...
1101
B
14 pole pairs
1110
B
15 pole pairs
1111
B
16 pole pairs
Pulse-Width-Modulation Mode: Error Indication
xx0x
B
error indication enabled
xx1x
B
error indication disabled
Incremental Interface Mode: Absolute Count
Interface counts to absolute value at startup
x0xx
B
absolute count enabled
x1xx
B
absolute count disabled
SPC Mode: Total Trigger Time
Duration of the master pulse to trigger SPC output
0000
B
90*UT
0100
B
t
mlow
+ 12 UT
Reset: derivate-specific
IFAB_RES (multi-purpose) 4:3 w Pulse-Width-Modulation Mode: Frequency
Selection of PWM frequency.
00
B
244 Hz
01
B
488 Hz
10
B
977 Hz
11
B
1953 Hz
Incremental Interface Mode: IIF resolution
00
B
12bit, 0.088° step
01
B
11bit, 0.176° step
10
B
10bit, 0.352° step
11
B
9bit, 0.703° step
SPC Mode: SPC Frame Configuration
00
B
12bit angle
01
B
16bit angle
10
B
12bit angle + 8bit temperature
11
B
16bit angle + 8bit temperature
Reset: derivate-specific
Field Bits Type Description