Datasheet, Volume 1 19
Introduction
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
®
64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
IMC Integrated Memory Controller
Intel
®
64 Technology 64-bit memory extensions to the IA-32 architecture
Intel
®
DPST Intel
®
Display Power Saving Technology
Intel
®
FDI Intel
®
Flexible Display Interface
Intel
®
TXT Intel
®
Trusted Execution Technology
Intel
®
Virtualization
Technology
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
Intel
®
VT-d
Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
IOV I/O Virtualization
ITPM Integrated Trusted Platform Module
LCD Liquid Crystal Display
LVDS
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
NCTF
Non-Critical to Function. NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
PCH
Platform Controller Hub. The new, 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PECI Platform Environment Control Interface
PEG
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
Processor The 64-bit, single-core or multi-core component (package).
Processor Core
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Processor Graphics Intel
®
Processor Graphics
Rank
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a SO-
DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
TAC Thermal Averaging Constant.
TDP Thermal Design Power.
Term Description
Intel
To Next Page
Loading...
Need help?
General
