Intel M10JNP2SB - Appendix C. POST Code Errors

Intel® Server Board M10JNP2SB User Guide
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Appendix C. POST Code Errors
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. In the
Intel® Server Board M10JNP2SB the POST codes are visible on the lower right part of the screen during
POST. The following table describes the type of checkpoints that may occur during the POST portion of the
BIOS:
Checkpoint Ranges
Status Code Range
Description
0x01 – 0x0B
SEC execution
0x0C – 0x0F
SEC errors
0x10 – 0x2F
PEI execution up to and including memory detection
0x30 – 0x4F
PEI execution after memory detection
0x50 – 0x5F
PEI errors
0x60 – 0x8F
DXE execution up to BDS
0x90 – 0xCF
BDS execution
0xD0 – 0xDF
DXE errors
0xE0 – 0xE8
S3 Resume (PEI)
0xE9 – 0xEF
S3 Resume errors (PEI)
0xF0 – 0xF8
Recovery (PEI)
0xF9 – 0xFF
Recovery errors (PEI)
Standard Checkpoints
SEC Phase
Status
Code
Description
0x00
Not used
Progress Codes
0x01
Power on. Reset type detection (soft/hard).
0x02
AP initialization before microcode loading
0x03
North Bridge initialization before microcode loading
0x04
South Bridge initialization before microcode loading
0x05
OEM initialization before microcode loading
0x06
Microcode loading
0x07
AP initialization after microcode loading
0x08
North Bridge initialization after microcode loading
0x09
South Bridge initialization after microcode loading
0x0A
OEM initialization after microcode loading
0x0B
Cache initialization