KEB combivert R6-S - Digital In- and Outputs

Seite 3.4 - 2 COMBIVERT R6-S © KEB, 2008-02
Digital in- and outputs
3.4.1 Short description digital inputs .............................................................................................. 3.4 - 3
3.4.2 Digital inputs in PNP control (di.00) ...................................................................................... 3.4 - 4
3.4.3 Set digital inputs per software (di.01, di.02) ......................................................................... 3.4 - 4
3.4.4 Input terminal state (ru.21), internal input state (ru.22) ........................................................ 3.4 - 5
3.4.5 Digital noise lter (di.03) .........................................................................................................3.4 - 6
3.4.6 Invert the inputs (di.04)............................................................................................................3.4 - 6
3.4.7 Input trigger (di.05) ..................................................................................................................3.4 - 6
3.4.8 Strobe-dependent inputs (di.06, di.07, di.08) ........................................................................3.4 - 6
3.4.9 Reset / input selection (di.09) and neg. slope for reset inputs (di.10) ................................ 3.4 - 8
3.4.10 Assignment of the inputs ........................................................................................................ 3.4 - 8
3.4.11 Software-ST and locking of the control release ..................................................................3.4 - 10
3.4.12 Short description - digital outputs ....................................................................................... 3.4 - 11
3.4.13 Output signals / hardware ..................................................................................................... 3.4 - 12
3.4.14 Output lter (do.43, do.44) ....................................................................................................3.4 - 12
3.4.15 Conditions (do.00...do.07) .....................................................................................................3.4 - 13
3.4.16 Invert conditions for ags 0...7 (do.08...do.15) .................................................................... 3.4 - 15
3.4.17 Selection of the conditions for ags 0...7 (do.16...do.23) ................................................... 3.4 - 15
3.4.18 AND/OR connection of the conditions (do.24) .................................................................... 3.4 - 15
3.4.19 Invert of ags (do.25...do.32) ...............................................................................................3.4 - 16
3.4.20 Selection of ags (do.33...do.40) ..........................................................................................3.4 - 16
3.4.21 AND / OR connection of the ags (do.41) ............................................................................ 3.4 - 17
3.4.22 Output terminal state (ru.25) and digital output state (ru.80) ............................................ 3.4 - 18
3.4.23 Hardware output allocation (do.51) ...................................................................................... 3.4 - 18