Keysight Technologies M9010A - 10 Mhz Reference Clock Source

PXIe Chassis Family
User Guide
77
7 10 MHz Reference Clock Source
PXIe Chassis timing is based on a 10 MHz reference clock. The 10 MHz Reference
Clock can originate from any of the three sources listed below. These sources are
listed in low to high precedence order if multiple 10 MHz reference clock sources
are available:
– Chassis internal 10 MHz clock
– Rear panel 10 MHz clock (connected to the chassis through a BNC
connector)
– System timing slot (slot 10) 10 MHz clock
For example, if both a rear panel 10 MHz clock and a system timing slot 10 MHz
clock are provided, the system timing slot 10 MHz clock will be used by the
chassis to generate its internal timing signals. There are no means to override
this order of precedence; for example, there are no means to select the rear panel
10 MHz clock if a system timing module (in slot10) clock is present. The module
in the system timing slot would need to be removed from the chassis in order to
activate selection of the rear panel 10 MHz clock.
The following Using the SFP to Monitor the 10 MHz Reference diagram shows
how to monitor the 10 MHz clock.
The chassis references either the rear panel 10 MHz clock or the
system timing slot 10 MHz clock as long as the clock frequency
remains within the specification range of ±100 ppm. The chassis
clocks are undefined if the reference clock is outside of this range.
On the M9010A chassis, if you use a Reference Clock signal with
an amplitude of < 500mVpp, the Reference Clock alarm may
repeatedly trigger even after clearing it. The chassis PLL may be
locked to the Reference Clock signal but the signal may have
excessive jitter. If this situation occurs, you need to increase the
clock signal amplitude.