100 Chapter 4: Matrox Solios hardware reference
Memory
As a standard feature, all Matrox Solios boards except Matrox Solios eCL/XCL-B
and Matrox Solios eCL/XCL-F support up to 256 Mbytes of linearly addressable,
DDR SDRAM used as acquisition memory. This memory has a bandwidth of up
to 1.6 Gbytes/sec when the optional Processing FPGA is installed, and up to
1.32 Gbytes/sec without the optional Processing FPGA installed.
As a standard feature, Matrox Solios eCL/XCL-B and eCL/XCL-F also support
acquisition memory. However, Matrox Solios eCL/XCL-B supports up to
128 Mbytes of linearly addressable DDR SDRAM, with a bandwidth of up to
800 Mbytes/sec. Matrox Solios eCL/XCL-F supports up to 256 Mbytes of
110 MHz SDRAM with a bandwidth of 1.76 Gbytes.
Optional memory If the optional Processing FPGA is installed on the board, Matrox Solios supports
up to 256 Mbytes of additional DDR SDRAM and either four or eight Mbytes
of QDRII SRAM. The Processing FPGA has an 83.3 MHz 64-bit DDR controller
BGR-to-YUV • Y = 0.114B + 0.587G +0.0229R
• U = 0.500B - 0.331G - 0.169R + 2
(res-1)
• V = -0.081B - 0.419G + 0.500R + 2
(res-1)
BGR-to-YCbCr (SDTV)
• Y = 0.098B + 0.504G + 0.257R + 2
(res-4)
• Cb = 0.439B - 0.291G - 0.148R + 2
(res-1)
• Cr = -0.071B - 0.368G + 0.439R + 2
(res-1)
BGR-to-YCbCr (HDTV)
• Y = 0.062B + 0.614G + 0.183R + 2
(res-4)
• Cb = 0.439B - 0.338G - 0.101R + 2
(res-1)
• Cr = -0.040B - 0.399G + 0.439R + 2
(res-1)
YCbCr-to-YUV
(SDTV and HDTV)
• Y = 1.164Y - 1.164 X 2
(res-4)
• U = 1.138Cb - 1.138 X 2
(res-4)
• V = 1.138Cr - 1.138 X 2
(res-4)
1. Some of these equations depend on the input pixel resolution (res), which is either 8, 10, or 16.
To Next Page
Loading...
