Matrox Solios Series - Page 117

Board summary 117
- An LVDS/TTL CSYNC input or HSYNC input/output.
- An LVDS/TTL VSYNC input/output.
- A TTL auxiliary input signal (trigger, field polarity, or user-defined input). See
the Matrox Solios hardware reference chapter for supported configurations.
- A TTL auxiliary output signal (exposure or user-defined output). See the
Matrox Solios hardware reference chapter for supported configurations.
- Two TTL/LVDS auxiliary output signals (exposure, synchronization, or
user-defined output). See the Matrox Solios hardware reference chapter for
supported configurations.
- An opto-isolated auxiliary input signal (trigger or user-defined input). See the
Matrox Solios hardware reference chapter for supported configurations.
- RS-232 serial port.
-Bi-color status LED.
• One, two, or four 1024 entry 8- or 16-bit programmable LUTs, depending on
the board.
• 64/128/256 Mbytes of 83 MHz DDR SDRAM used as acquisition memory.
1.32 Gbytes/sec of memory bandwidth. Note that when the optional Processing
FPGA is installed, these numbers increase to 100 MHz and 1.6 Gbytes/sec
respectively.
• Eight TTL/LVDS auxiliary input signals (trigger, field polarity, data valid,
timer-clock, synchronization, and/or user-defined input). See the Matrox Solios
hardware reference chapter for supported configurations.
• Supports a 64-bit 66/100/133 MHz 3.3 V PCI-X (or a 32/64-bit 33/66 MHz
3.3 V or 5 V conventional PCI) Host interface for Matrox Solios XA, a x4 or
greater PCIe Host interface for Matrox Solios eA, and a x1 or greater Host interface
for Matrox Solios eA Single.