Mitsubishi Electric Q170MSCPU-S1 - Q170 MSCPU System Internal Configuration

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2 SYSTEM CONFIGURATION
2.1.2 Q170MSCPU System internal configuration
(1) What is Multiple CPU system for Q170MSCPU ?
A Multiple CPU system for Q170MSCPU is a system in which the PLC CPU area
and Motion CPU area are connected with the Multiple CPU high speed bus in
order to control the I/O modules and intelligent function modules.
PLC CPU area is fixed as CPU No.1, and Motion CPU area is fixed as CPU No.2.
In addition, the Motion CPU area controls the servo amplifiers connected by
SSCNET
cable.
24VDC
Motion module
(Proximity dog signal, manual
pulse generator input)
Device memory
Multiple CPU
high speed
transmission
memory
PLC control
processor
Power supply
PLC CPU area (CPU No.1 fixed)
Motion controlle
r
Multiple CPU
high speed
transmission
memory
Device memory
Motion control
processor
Motion CPU area (CPU No.2 fixed)
Multiple CPU
high speed
bus
Q series PLC system bus
Personal computer
GX Works2
MT Developer2
PLC I/O module
(DI/O)
PLC intelligent
function module
(A/D, D/A, Network etc.)
Manual pulse generator/Incremental
synchronous encoder 1 module
P
Input signal/Mark detection input signal (4 points)
Output signal (2 points)
PERIPHERAL I/F
Personal computer
MT Developer2
Forced stop input (24VDC)
SSCNET (/H)
Servo
amplifier
M
Servo
motor
Servo external
input signals
(FLS, RLS, DOG)
M
(a) The device memory is the memory area for the bit devices (X, Y, M, etc.)
and word devices (D, W, etc.).
(b) The Multiple CPU high speed transmission memory between the PLC CPU
area and Motion CPU area can be communicated at 0.88ms cycles.