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MELSEC-Q
5   DETAILS AND SETTING OF FUNCTIONS 
 
5.9 Count Response Delay Time 
The count value of the QD60P8-G is delayed for the following reasons. Please take 
this into consideration when using the module as a counter. 
•  A delay occurs due to the scan time of a sequence program at the time of count start 
processing using the count enable (Y18 to Y1F). 
 
•  A delay occurs due to the control cycle (10ms). A maximum of 20ms (one control 
cycle 
 2) delay occurs from when the count enable (Y18 to Y1F) is turned ON/OFF 
until the "input pulse value" of the buffer memory is displayed. Similarly, a delay also 
occurs at a counter reset request. 
 
The calculation expression of the delay time is as indicated below. 
 
Maximum delay time [ms] = (1 scan time + 20) [ms]