Philips Q528.1E - Diagram B05, PNX5050 (IC 7 C00)

Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 151Q528.1E LA 9.
9.10.7 Diagram B05, PNX5050 (IC 7C00)
Figure 9-29 Pin configuration
Block Diagram
Pin Configuration
H_16800_129.eps
090507
MAIN MEMORY
INTERFACE
DDR SDRAM
4 : 2 : 2 VIDEO IN
AUDIO IN
SPDIF IN
BOOT, RESET,
CLOCKS
SCALER,
DEINTERLACER
INSTR
CACHE
300 MHz
32-BIT
CPU
DATA
CACHE
2D DRAWING
ENGINE
XIO INTERFACE
FLASH
MEMORY
MISCELLANEOUS
I/O,
TIMERS,
COUNTERS
I
2
C
4 : 4 : 4 VIDEO IN
PICTURE
IMPROVEMENT
IMAGE
COMPOSITION
AUDIO OUT
LCD
OUTPUTROUTER
SD video ITU-R BT.656
I
2
S-bus audio
27 MHz
I
2
C-bus
GPIO
SPDIF audio
HD video YUV
4 : 2 : 2
HD / PC YUV /
RGB 4 : 4 : 4
24-bit RGB/
30-bit RGB
I
2
S-bus audio
SPDIF audioSPDIF OUT
A
C
E
G
J
L
N
R
U
W
AA
AC
AE
B
D
F
H
K
M
P
T
V
Y
AB
AD
AF
2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
PNX5050