Raisecom RC3000 - Page 66

www.raisecom.com User Manual
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PCB version: REV A.3 CPLD version: REV 1.0
Signal: None Receive Phase:Positive Transmit Phase:Positive
Channel: Main Channel
Local Loopback: No Loopback Remote Loopback: No Loopback
BER Test: Enable
7235 Auto Adjust Phase: Enable
Adjust Receive Phase: Enable(Clock Down)
DTR State: 0(Ready) RTS State: 0(Ready)
DCD State: 1(Unready) CTS State: 1(Unready)
BER test result: Normal
Note: parameters of phase adjustment: positive and negative;
Channel: main channel & Single channel
Loopback Set: No Loopback & Loopback
BER Test: Disable & Enable
Auto to Adjust Phase for Transmit: Enable & Disable
To Adjust Receive Phase: Enable & Disable
Status of DTR, RTS, DCD, CTS: Ready & Unready
BER test result: Normal & Abnormal; if you disable BER test, there will not be this item.
Sub-card type 7 V24 data user card:
Type: 7 V24 User Board Timeslot Number: 8 Set Mode: Hardware
PCB version: REV B.0 CPLD version: REV 1.0
Signal: None
Secondary CPLD version: REV1.0
Port 1: Bandwidth: 128kbps
Receive Phase: Negative Transmit Phase:Positive
Port 2: Bandwidth: 64kbps
Receive Phase: Negative Transmit Phase:Positive
Port 3: Bandwidth: 128kbps
Receive Phase: Negative Transmit Phase:Positive
Port 4: Bandwidth: 64kbps
Receive Phase: Negative Transmit Phase:Positive
Sub-card type 8 Ethernet data user card:
Type: 8 Ether Net Board Timeslot Number: 0 Set Mode: Hardware
PCB version: REV A.0 CPLD version: REV 1.0
Signal:None
Channel:Main Channel
Band Width Buffer:>512Kbps