R&S EM510 - SCPI Status Register Structure and Sections

Remote Control via LAN EM510
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5.5.1 Structure of an SCPI Status Register
Each SCPI register consists of 5 sections, each having a width of 16 bits and different functions (see
Figure 5-4). The individual bits are independent of each other, i.e. a bit number being valid for all five
sections is assigned to each hardware status. Bit 3 of the STATus:OPERation register, for example, is
assigned to the hardware status "SWEeping" in all five sections. Bit 15 (the most significant bit) is set to
zero for all sections. Thus the contents of the register sections can be processed by the controller as
positive integers.
General status register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
+
&
&
&
&
&
&
&
&
&
.
&
1
CONDition
PTRan-
sition
NTRan-
sition
ENABle
0
1
2
3
4
5
6
7
8
.
15
0
1
2
3
4
5
6
7
8
.
15
0
1
2
3
4
5
6
7
8
.
15
0
1
2
3
4
5
6
7
8
.
15
to the higher-order register
& = logical AND
1
= logical OR of all bits
0
1
2
3
4
5
6
7
8
.
15
EVENlt
Figure 5-4: Status register model
CONDition section the CONDition section of a register directly reflects the state of the hardware.
This register section can only be read. Its contents are not changed during
reading.
As an alternative, a bit in a CONDition register can also contain the summary
information of a further status register connected in front. In this case, the bit
is cleared on reading out the status register.
PTRansition section the Positive-TRansition section acts as an edge detector. When a bit of the
CONDition section is changed from 0 to 1, the associated PTR bit decides
whether the EVENt bit is set to 1.
PTR bit =1: the EVENt bit is set.
PTR bit =0: the EVENt bit is not set.
This section can be written into and read in any way. Its contents are not
changed during reading.