Renesas R8C series User Manual

R8C/1A Group, R8C/1B Group 12. Interrupts
Rev.1.30 Dec 08, 2006 Page 84 of 315
REJ09B0252-0130
Figure 12.4 INT0IC Register
INT0 Interrupt Control Register
(2)
Symbol Address After Reset
INT0IC
005Dh XX00X000b
Bit Symbol Bit Name Function RW
NOTES :
1.
2.
3.
4.
—
(b7-b6)
—
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
—
(b5)
Reserved bit Set to 0.
RW
POL
Polarity sw itch bit
(4)
0 : Selects falling edge.
1 : Selects rising edge.
(3)
RW
IR
Interrupt request bit 0 : Requests no interrupt.
1 : Requests interrupt.
RW
(1)
ILV L0 RW
Interrupt priority level select bits
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILV L1 RW
ILV L2 RW
b0
0
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to
12.5.6 Changing Interrupt Control Registers.
If the INTOPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to
12.5.5 Changing Interrupt
Sources.
b7 b6 b5 b4 b3 b2 b1

Renesas R8C series Specifications

General

Brand	Renesas
Model	R8C series
Category	Computer Hardware
Language	English