Renesas R8C series

R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.30 Dec 08, 2006 Page 4 of 315
REJ09B0252-0130
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
Figure 1.1 Block Diagram
A/D converter
(10 bits
× 4 channels)
UART or
clock synchronous serial I/O
(8 bits
× 1 channel)
R8C/Tiny Series CPU core
8
4
1 3
Timers
Timer X (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
System clock generator
XIN-XOUT
High-speed on-chip
oscillator
Low-speed on-chip
oscillator
Memory
Watchdog timer
(15 bits)
ROM
(1)
RAM
(2)
Multiplier
R0H R0L
R1H
R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports Port P1
Port P3 Port P4
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
UART
(8 bits
× 1 channel)
SSU (8 bits × 1 channel)
or I
2
C bus
Peripheral Functions