Renesas R8C series

R8C/1A Group, R8C/1B Group 12. Interrupts
Rev.1.30 Dec 08, 2006 Page 99 of 315
REJ09B0252-0130
Figure 12.19 Registers AIER, and RMAD0 to RMAD1
A
ddress Match Interrupt Enable Registe
r
Symbol Address After Reset
AIER
0009h 00h
Bit Symbol Bit Name Function RW
AIER1
Address match interrupt 1 enable bit
AIER0
0 : Disable
1 : Enable
RW
b2 b1 b0
Address match interrupt 0 enable bit
—
(b7-b2)
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
b7 b6 b5 b4
0 : Disable
1 : Enable
RW
b3
Address Match Interrupt Register i(i = 0,1)
b0
Symbol Address After Reset
RMAD0
0012h-0010h X00000h
RMAD1
0016h-0014h X00000h
Setting Range RW
(b15)
b7
(b8)
b0 b7
00000h to FFFFFh
Function
RW
—
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Address setting register for address match interrupt
(b23)
b7
(b16)
b0
(b19)
b3